ULP Clock Source / Frequency

[cnlohr]

I can't find any information on how to set the ULP's clock source. I am wondering if there is any way to clock it up at 24 MHz, then it should be possible to use the ULP as a low-speed USB device. I tried a number of things on the main ESP32 core, but because of the huge latency when reading GPIO and difficulty with the I2S bus, I could never get full-speed USB working.

Just wondering if I can run the ULP off some divisor of the main clock while the system is in regular run mode. It would have to be within about 2% clock because of needing to send stuff back to a host.

[ESP_igrr]

This is described in "low-power management" chapter of the TRM. ULP is clocked from RTC_FAST_CLK, which is either internal 8MHz oscillator (divided by n, configurable), or XTAL (usually 40MHz) divided by 4.
There doesn't seem to be an option to derive RTC_FAST_CLK from a different source.

[cnlohr]

Bummer. I don't think I could reasonably slip what I want to do into 10 MHz. Mindbogling that the V-USB people can do it in 12 as it is.

Well, tuck that into the wish list... along with:

(1) /really/ fast I2S
(2) Mapping the xtensa MISC registers to GPIO

Charles