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Dual core watchdog reset issue

http://esp32.io/viewtopic.php?f=2&t=37724

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Dual core watchdog reset issue

Posted: Wed Jan 10, 2024 12:43 pm
by Mohit.Nama
hello everyone ,
i just wnant to check the condtion . if core1 task is hang up due to some resone ...then it should restart the task of that core (core1).
suggest tha canges in code .
here watchdog is triggered but not restarting the core1 task .

Code: [Select all] [Expand/Collapse]
  1. [/*
  2. Aim : to test two core working saparetly SPI ,UART 1,UART2 ;
  3.  
  4. Result :
  5. code ruunig fine with all uaret wokring ,Read write togther
  6. */
  7. #include "freertos/FreeRTOS.h"
  8. #include "esp_wifi.h"
  9. #include "esp_system.h"
  10. #include "esp_event.h"
  11. #include "esp_event.h"
  12. #include "nvs_flash.h"
  13. #include "driver/gpio.h"
  14.  
  15. #include <stdlib.h>
  16. #include <stdio.h>
  17. #include <string.h>
  18.  
  19. #include "esp_flash.h"
  20. #include "esp_flash_spi_init.h"
  21. #include "esp_partition.h"
  22. #include "esp_vfs.h"
  23. #include "esp_vfs_fat.h"
  24. #include "esp_system.h"
  25. #include "soc/spi_pins.h"
  26.  
  27. #include "driver/gpio.h"
  28. #include "driver/uart.h"
  29.  
  30. //-----watchdog
  31. #include "esp_task_wdt.h"
  32.  
  33.  
  34. #define BUF_SIZE (1024)
  35.  
  36. uint32_t count=0 ;
  37.  
  38. // h2 and c2 will not support external flash
  39. #define EXAMPLE_FLASH_FREQ_MHZ      40
  40.  
  41. static const char *TAG = "Flash";
  42.  
  43. // Pin mapping
  44. // ESP32 (VSPI)
  45.  
  46. #define HOST_ID  SPI3_HOST
  47. #define PIN_MOSI GPIO_NUM_2 //---
  48. #define PIN_MISO GPIO_NUM_19//---
  49. #define PIN_CLK  GPIO_NUM_4
  50. #define PIN_CS   GPIO_NUM_5
  51. #define SPI_DMA_CHAN SPI_DMA_CH_AUTO
  52.  
  53. esp_flash_t* ext_flash;
  54. //----MY Variable
  55. int SR_NO= 1,Read_SR_N0=0;
  56. float data=100.00,Read_data=0;
  57. uint32_t address=0x00,Read_add=0x00;
  58.  
  59. static esp_flash_t* init_spi_flash(void){
  60.  
  61.  //-----set spi pin configurataion
  62.  const spi_bus_config_t bus_config = {
  63.         .mosi_io_num = PIN_MOSI,
  64.         .miso_io_num = PIN_MISO,
  65.         .sclk_io_num = PIN_CLK,
  66.         //.quadhd_io_num = PIN_HD,
  67.         //.quadwp_io_num = PIN_WP,
  68.     };
  69.  
  70.  const esp_flash_spi_device_config_t device_config = {
  71.         .host_id = HOST_ID,
  72.         .cs_id = 0,
  73.         .cs_io_num = PIN_CS,
  74.         .io_mode = SPI_FLASH_DIO,
  75.         .freq_mhz = EXAMPLE_FLASH_FREQ_MHZ,
  76.     };
  77.  
  78. ESP_LOGI(TAG, "Initializing...SPI Flash");
  79. // Initialize the SPI bus
  80. ESP_ERROR_CHECK(spi_bus_initialize(HOST_ID, &bus_config, SPI_DMA_CHAN));
  81.   // Add device to the SPI bus
  82.  
  83. ESP_ERROR_CHECK(spi_bus_add_flash_device(&ext_flash, &device_config));
  84.  
  85.  // Probe the Flash chip and initialize it
  86. esp_err_t err = esp_flash_init(ext_flash);
  87.  
  88. if (err != ESP_OK) {
  89.         ESP_LOGE(TAG, "Failed to initialize SPI Flash: %s (0x%x)", esp_err_to_name(err), err);
  90.         return NULL;
  91.                     }
  92.  
  93.  // Print out the ID and size
  94.     uint32_t id;
  95.     ESP_ERROR_CHECK(esp_flash_read_id(ext_flash, &id));
  96.     ESP_LOGI(TAG, "Initialized SPI Flash, size=%" PRIu32 " KB, ID=0x%" PRIx32, ext_flash->size / 1024, id);
  97.  
  98.     return ext_flash;
  99.  
  100. }
  101. void Core_1_Task(void* parameter){
  102.  esp_task_wdt_reset();  
  103. ESP_LOGI("Core1", "Satrt\n");
  104. esp_task_wdt_add(NULL);
  105. while(1){
  106.  
  107.  
  108.  
  109. if(address>Read_add){
  110.  
  111. esp_flash_read(ext_flash, &Read_SR_N0, Read_add, sizeof(Read_SR_N0));
  112. Read_add+=sizeof(Read_SR_N0);
  113. esp_flash_read(ext_flash, &Read_data, Read_add, sizeof(Read_data));
  114. Read_add+=sizeof(Read_data);
  115. Read_add++;
  116. ESP_LOGI("core1 SPI-R", "SR_NO %d ,data %f\n",Read_SR_N0,Read_data);
  117. }
  118.  
  119. //vTaskDelay(1000 / portTICK_PERIOD_MS);
  120. //printf("Core0 \n");
  121. // printf("Core1 \n");
  122.    if(SR_NO==10){
  123.    ESP_LOGI("Core1", "hang tes\n");
  124.    while (1)
  125.    {
  126.     /* code */
  127.    }
  128.    
  129.  
  130.    }
  131. vTaskDelay(2000/ portTICK_PERIOD_MS);
  132. esp_task_wdt_reset();
  133. }
  134.                                 }
  135.  
  136. void Core_0_Task(void* parameter){
  137.    
  138.    
  139.    
  140.    while(1){
  141.    
  142.    esp_flash_write(ext_flash, &SR_NO, address, sizeof(int));
  143.    address+=sizeof(int);
  144.    esp_flash_write(ext_flash, &data, address, sizeof(float));
  145.    address+=sizeof(float);
  146.    ESP_LOGI("Core0 SPI-W", "SR_NO %d ,data %f\n",SR_NO,data);
  147.    address++;
  148.    SR_NO++;
  149.    data++;
  150.  
  151.    vTaskDelay(2000 / portTICK_PERIOD_MS);
  152.    
  153.     }
  154. }
  155. void app_main(void)
  156. {
  157.  
  158.     // Set up SPI bus and initialize the external SPI Flash chip
  159.     esp_flash_t* flash = init_spi_flash();
  160.     if (flash == NULL) {
  161.         return;
  162.  
  163.                        }
  164.      
  165.     esp_flash_erase_chip(flash);
  166.     ESP_LOGI("Code", "Start\n");
  167.     xTaskCreatePinnedToCore(Core_1_Task, "core1", 1024*5, NULL, 2, NULL, 1);
  168.     xTaskCreatePinnedToCore(Core_0_Task, "core0", 1024*3, NULL, 0, NULL, 0);            
  169.  
  170. }
  171. ]
  172. logs
  173.  
  174. E (83268) task_wdt: Task watchdog got triggered. The following tasks/users did not reset the watchdog in time:
  175. E (83268) task_wdt:  - core1 (CPU 1)
  176. E (83268) task_wdt:  - IDLE (CPU 1)
  177. E (83268) task_wdt: Tasks currently running:
  178. E (83268) task_wdt: CPU 0: IDLE
  179. E (83268) task_wdt: CPU 1: core1
  180. E (83268) task_wdt: Print CPU 1 backtrace
  181.  
  182.  
  183. Backtrace: 0x40084E26:0x3FFB13B0 0x400829DD:0x3FFB13D0 0x400D5629:0x3FFB6FD0 0x40088739:0x3FFB7000
  184. 0x40084e26: esp_crosscore_isr at C:/Users/mohit/esp/esp-idf/components/esp_system/crosscore_int.c:96
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Re: Dual core watchdog reset issue

Posted: Thu Jan 11, 2024 1:42 am
by ESP_Sprite
It's generally not a good idea to 'restart' a task - if it uses any shared resources (memory, peripherals, locks, semaphores) it's pretty hard to impossible to make sure those are freed correctly. Rather, the watchdog timer gives the option to restart the entire chip - you can enable that in menuconfig. I'd suggest you find another way to catch a 'hung task' situation - e.g. add timeouts to blocking functions and throw an error if that timeout is reached.

Re: Dual core watchdog reset issue

Posted: Thu Jan 11, 2024 8:50 am
by Mohit.Nama
i know that's not i good idea , but i want to do .....as i am asking .. could you please help .
i want to restart that thask on TWDT trigger .....

Re: Dual core watchdog reset issue

Posted: Thu Jan 11, 2024 8:58 am
by ESP_Sprite
Mohit.Nama wrote: ↑
Thu Jan 11, 2024 8:50 am
 i know that's not i good idea , but i want to do .....as i am asking .. could you please help .
No, sorry.

Re: Dual core watchdog reset issue

Posted: Thu Jan 11, 2024 11:24 am
by Mohit.Nama
sorry for west your time.
suggest how to do :
1. how to record reason or status of cpu.
2. How to restart after TWDT triggered , is it neccesry to restart ,is there any ohther way to reset the tiggre state .

Re: Dual core watchdog reset issue

Posted: Fri Jan 12, 2024 2:46 am
by ESP_Sprite
What the task WDT does is configurable in menuconfig (if you're using esp-idf); resetting the chip is one of the options there. You can get the reset reason here.

Re: Dual core watchdog reset issue

Posted: Fri Jan 12, 2024 10:34 am
by Mohit.Nama
Thanks for your valuable support ..
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