ESP32 Forum

I read some of the esp32 docs and it says external flash is memory is up to 16MB(128 Mb). Is that the limitation of the physical spi interface on the chip or software.Because i have read various different brand flash chips and they support the same instruction set even those above 256Mb(32 MB). So in theory a 32 MB chip should work in ( single,dual or Quad spi mode). The only difference is the 32 MB chip needs 4 bytes of address data. These chips also have an internal bank switch Mode using an Extended Address Register for compatibilty with devices with only 24 bit address mode. So is it possible to add extended support for chips above 16MB. I dont mind writing it myself. I know is possible by using bitbang gpio but i dont know if spi interface on chip is only 24 bits.

Using SPI2 or SPI3 you can use any device to write and read data from. However, afaik the ability to run code from a flash chip depends on the flash memory being address-mapped into the ESP's memory address space and accessed via MMU and cache using SPI0/1.
I believe the limiting factor here will be the address mapping because the TRM says "Due to this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB External SRAM."

is it possible to add extended support for chips above 16MB?

Probably not, given that the MMU basically needs to be in control of the SPI flash interface, and that it basically needs to be able to load code from flash at any time from the exact address where it expects to find it.

Yeh. In the docs also says the CPU uses 32 bit address so it should be able to address up to 4 GB. IF its the limitation of MMU, Might have to either use CPU SRAM as a cache and Load a chunk of data from higher size spi chips manually there then jmp to that code. Another way would be to monitor the Address line and Bank switch the chips bigger than 16 MB since for example a 32MB chip like 25Q25635FN ahas a compatibilty function where you can address the 32MBs as 2 banks of 16 MB.