I am using an ESP32 -WROVER-E module for my project. What I am trying to do, is to run an I2C-Slave task on one core, while a WIFI task runs on the other. I do this, in order to simultaneously be able to answer to an I2C-Master querying my device for values, as well as communicating to another system via TCP-Sockets in a local network.
So far, I have succesfully developed bitbanging-code for my device to act as an I2C-Slave. I know, that the ESP32 has two I2C hardware peripherals. However, I need to be able to listen to I2C messages directed to all I2C addresses. This is not possible using the hardware modules, since they automatically filter out messages directed to different I2C addresses than the one assigned to them.
When I run this code on CPU1, without any noteable other tasks (except for of course the IDLE Task etc.) running on CPU0, my ESP32 is able to answer to the I2C-Master device without fail. I have established a connection and let it run for an hour. Afterwards I analyzed the data and found no errors in it at all. The I2C-Master is also an ESP32-WROVER-E, that queries at maximum I2C frequency using their hardware peripheral.
Now comes the issue: Apart from the I2C task on CPU1, I need a task for TCP socket communication, as well as SNTP time synchronization on CPU0. I have pinned all system tasks (everything configurable I found in menuconfig), as well as the LWIP task to CPU0. I have also turned off interrupts and the watchdog task on CPU1. However, when I run this setup, the I2C communication only seems to work around 95% of the time. Every now and then, something interferes with my bitbanging task which causes a reading timeout or fail on the I2C-Master side. This interference is at irregular time-intervals.
I have checked task status with esp-idf tracing functions and no task is scheduled on CPU1 at any point to interrupt my bitbanging task as far as I can tell. The bitbanging task consists of a big loop, that queries GPIO levels and saves them to a variable. I have put all the functions of the Bitbanging task into IRAM by assigning the IRAM_ATTR. I have put the static variables of the Bitbanging task into DRAM by assigning the DRAm_ATTR. This was done in order to avoid concurrent access to Flash memory, which I thought could be the cause for this interference.
Does Anybody have a clue, what could cause this interference?
TLDR; CPU0 runs WIFI task(s) and CPU1 runs I2C-Slave bitbanging task. When I only run the I2C task on CPU1, everything works fine. As soon as I concurrently run the WIFI task(s) on CPU0, it interferes with my isolated task on CPU1. CPU1 has all interrupts and watchdog turned off.
WIFI STACK on CPU0 interferes with CPU1
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Re: WIFI STACK on CPU0 interferes with CPU1
Hard to say. There's delays that could come from the flash being occupied when cache needs to be refilled; you could possibly work around that by putting as much time-critical code in IRAM as possible. There's also some hardware workarounds on the ESP32 chips (see the ECO list) that can cause some delay, but I'm not sure if there is a way to get rid of those.
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