ESP32 Forum

I have a program running that I enabled sysview tracing (all freeRTOS events turned on).

When I enable the sysview on the host side, all my timings are terrible.

I have a timer firing every 550 us, in the timer interrupt I start a SPI transaction. The SPI completes and I handle it and setup for
the next timer to fire off and start the SPI again. When I am not trying to get the sysview info (esp32 sysview stop). Then my timing
is very solid. There are actually 2 interrupts one for each of 2 SPI devices and one takes 9us and the other takes 10us.

When I start to gather the sysview info (esp32 sysview start file://ble1.SVDat file://ble2.SVDat 1) then the sysview data says my
interrupts are taking 64ms. But that can't be right, I have a logic analyzer on my signals and it is taken 64ms now. When I disable the
sysview (esp32 sysview stop) eveything goes back to looking great. Also Bluetooth connectivity drops when I have the sysview turned on
as well.

I was using a SEGGER j-link, But I just got my ESP WROVER kit and tried using that since I can't get my SEGGER to work above 3Mhz and
the WROVER goes up to 20Mhz. But nothing changed. Is there anything I can do to get a good trace without affecting the actual running?

On the plus side, I love the ESP-32 and this tracing interface for logging, system view and tracing is great Thanks Espressif.

I am including the sysview files, I can also get screen shots of my analyzer showing the timing.

What JTAG clock speed do you have configured in openocd?

For the Segger I have 3Mhz for the WROVER it is 20Mhz. here is the output from the WROVER
openocd -f ~/esp32.cfg
Open On-Chip Debugger 0.10.0-dev-gb5ec731 (2017-07-20-09:41)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 20000 kHz
force hard breakpoints
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 20000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32: Debug controller was reset (pwrstat=0x5F, after clear 0x0F).
Info : esp32: Core was reset (pwrstat=0x5F, after clear 0x0F).

mishafarms, I will try to reproduce your problem.
Could you send me sdkconfig file you use for your project?
Did you enable additional data buffering in menuconfig Component config -> Application Level Tracing -> Size of the pending data buffer?

mishafarms, In order to help you I need the following info:
1) Version of IDF
2) Version of OpenOCD
3) sdkconfig.
4) OpenOCD log.

For now I would recommend you to use zero polling time instead of 1 ms period.