ESP32 Forum

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Open On-Chip Debugger 0.10.0-dev-gb5ec731f (2017-07-23-00:08)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
adapter speed: 200 kHz
force hard breakpoints
Info : clock speed 200 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)

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Info : accepting 'gdb' connection on tcp/3333
Info : Set current thread to 0x00000000, old= 0x00000000
Warn : xtensa_read_memory: esp32: target not halted
Error: Could not read FreeRTOS thread count from target

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ftdi_vid_pid 0x0403 0x6014

# 0x000f -> TMS, TCK, TDI, TDO
# 0x4000 -> ^LED
# 0x0010 -> GPIOL0 (grey)
# 0x0020 -> GPIOL1 (purpe)
# 0x0040 -> GPIOL2 (white)
# 0x0080 -> GPIOL3 (blue)

ftdi_layout_init 0x0008 0x400b

ftdi_layout_signal LED -ndata 0x4000

# We could use GPIOL0 and GPIOL1 for SRST resp. TRST.
# This is a guess how to do it:
# ftdi_layout_signal nSRST -data 0x0010 -oe 0x0010
# ftdi_layout_signal nTRST -data 0x0020 -oe 0x0020

ftdi_layout_signal GPIOL0 -data 0x0010 -oe 0x0010
ftdi_layout_signal GPIOL1 -data 0x0020 -oe 0x0020
ftdi_layout_signal GPIOL2 -data 0x0040 -oe 0x0040
ftdi_layout_signal GPIOL3 -data 0x0080 -oe 0x0080

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#
# Example configuration file to hook up an ESP32 module or board to a JTAG 
# adapter. Please modify this file to your local setup.
#
#


# Include the configuration for the JTAG adapter. We use the Tian TUMPA here.
# If you have a different interface, please edit this to include the 
# configuration file of yours.
source [find interface/ftdi/ftdi_usb.cfg]

# The ESP32 only supports JTAG.
transport select jtag

# The speed of the JTAG interface, in KHz. If you get DSR/DIR errors (and they
# do not relate to OpenOCD trying to read from a memory range without physical
# memory being present there), you can try lowering this.
adapter_khz 200

# With no variables set, openocd will configure JTAG for the two cores of the ESP32 and
# will do automatic RTOS detection. This can be be adjusted by uncommenting any of the
# following lines:

# Only configure the PRO CPU
#set ESP32_ONLYCPU 1
# Only configure the APP CPU
#set ESP32_ONLYCPU 2
# Disable RTOS support
#set ESP32_RTOS none
# Force RTOS to be FreeRTOS
set ESP32_RTOS FreeRTOS

#Source the ESP32 configuration file
source [find target/esp32.cfg]


# The TDI pin of ESP32 is also a bootstrap pin that selects the voltage the SPI flash
# chip runs at. When a hard reset happens (e.g. because someone switches the board off
# and on) the ESP32 will use the current TDI value as the bootstrap value because the
# JTAG adapter overrides the pull-up or pull-down resistor that is supposed to do the
# bootstrapping. These lines basically set the idle value of the TDO line to a 
# specified value, therefore reducing the chance of a bad bootup due to a bad flash
# voltage greatly.

# Enable this for 1.8V SPI flash
#esp108 flashbootstrap 1.8
# Enable this for 3.3V SPI flash
#esp108 flashbootstrap 3.3