ESP32 Forum

The CPU can access peripherals via DPORT address more efficiently than via AHB address. However,
DPORT address is characterized by speculative reads, which means it cannot guarantee that each read is
valid. In addition, DPORT address will upset the order of r/w operations on the bus to improve performance,
which may cause programs that have strict requirements on the r/w order to crash. On the other hand, using
AHB address to read FIFO registers will cause unpredictable errors. To address above issues please strictly
follow the instructions documented in ESP32 ECO and Workarounds for Bugs, specifically sections 3.3, 3.10,
3.16, and 3.17.

// There are several ways to read the DPORT registers:
// 1) Use DPORT_REG_READ versions to be SMP-safe in IDF apps.
// This method uses the pre-read APB implementation(*) without stall other CPU.
// This is beneficial for single readings.
// 2) If you want to make a sequence of DPORT reads to buffer,
// use dport_read_buffer(buff_out, address, num_words),
// it is the faster method and it doesn't stop other CPU.
// 3) If you want to make a sequence of DPORT reads, but you don't want to stop other CPU
// and you want to do it faster then you need use DPORT_SEQUENCE_REG_READ().
// The difference from the first is that the user himself must disable interrupts while DPORT reading.
// Note that disable interrupt need only if the chip has two cores.
// 4) If you want to make a sequence of DPORT reads,
// use DPORT_STALL_OTHER_CPU_START() macro explicitly
// and then use _DPORT_REG_READ macro while other CPU is stalled.
// After completing read operations, use DPORT_STALL_OTHER_CPU_END().
// This method uses stall other CPU while reading DPORT registers.
// Useful for compatibility, as well as for large consecutive readings.
// This method is slower, but must be used if ROM functions or
// other code is called which accesses DPORT without any other workaround.
// *) The pre-readable APB register before reading the DPORT register
// helps synchronize the operation of the two CPUs,
// so that reading on different CPUs no longer causes random errors APB register.

I'm not really sure what it stands for

• APB = Advanced Peripheral Bus (specification here)
• AHB = Advanced High-performance Bus. IIRC the ESP32 uses AHB-Lite (specification here)
• DPORT = Short for Data Port. The full name is Xtensa Local Memory Interface (XLMI) Port. Can't send you a spec here unfortunately as Xtensa specifications can only be obtained under an NDA.

and why there are two busses

• The same piece of physical memory/registers can be accessed by two or more ports
• The same piece of physical memory can be exclusive to a particular CPU, or shared (i.e., global) amongst multiple CPUs
• It is also possible that two ports can end up accessing the same child bus via an arbiter.

Are the APB bus and AHB bus the same thing and this is just a typo?

Also, where is the DPORT_INTERRUPT_DISABLE macro defined?

• There are a couple of HW bugs in the ESP32 (different bugs apply to different chip revisions) that can corrupt read/writes when the DPort is accessed under certain conditions (e.g., another CPU accessing a particular address range simultaneously).
• As per the comment, multiple workaround macros have been offered, each optimized to a particular type of usage (e.g., whether you're only reading a particular DPORT register, or need to read a series of DPORT registers
• The pre-readable APB register is one of the workarounds offered, where before a DPORT register is accessed, a random register (basically just a date register) is read first. Again, remember that SoCs can have multiple bus hierarchies, thus why reading the APB bus can affect the DPORT bus (thus working around the HW bug).