ESP32-S3 (Beta2) MARLIN_9_1B on ESP32-S3-Addax-1 V1.0 Specs & Datasheet

[rudi ;-)]

DevKIT
ESP32-S3-Addax-1_V1.0
Marlin-9-1B
522020
ESP32-S3 (Beta2)
engineering sample stage

ESP32-S3-Addax-1_V1.0.jpg (688.2 KiB) Viewed 36469 times

Hi Folks

perhabs you saw the News arround spotted in the wild.
i wounder why in this ESPRESSIF ESP32 BBS is no Info about the new ESP32-S3-Addax-1_V1.0 DevKIT which SoC ESP32-S3 have Marketing Status: Samples - and no one posted News about that you can request samples

and but cause there are many wrong solo details arround spotted and not in the right direction i feel to must show up few things from my desk and my side after few interna talks and pre-release datasheet got.

few asked for an ESP32-S3 Datasheet, there was answeres here and there to read like "i have it but i can not share sry ... "

Note:

if you sign an NDA for a Datasheet, the true is, you can't say " i have it but i can not share"
cause the NDA says you that you can not say "i have it..." cause the NDA fordbidden you to say what you have or what you not have, also the NDA would say to you, that you are not allowed to say, that you have an NDA...
so the story behind these possibles answeres are most translated " i have it but i want not show YOU"
..anyway interpretation space..

cause i have no NDA about this ESP32-S3 Datasheet - and cause it is not confidental - but only not public / not released at document folder / web and only a DRAFT, but i get it after asking for it -
you will get here few Infos and the pre release i can and want absoulutly share with you community after several receives, gets, contacts, research and also (wrong) founds in the wild:

Here you are:
- My printed ESP32-S3 Pre-Release Datasheet you find here in the meantime until it becomes a release at espressif web


3 things you have to note:
Note 1: The Footprint is not previewed cause it becomes a change in the Release - so do not design any PCB without the release version
Note 2: The Diagram is updated in the PreRelase V0.3.1 ( not need to publicy it cause it is only the Diagram updated ) you got from my archived Github ESP32DE
Note 3: Espressif can allways change things in the release version so be aware with any fixed things you want do for a pre work on PCB or anything - wait for the release PDF for this - read the pre release for an inside read.

- the latest Wi-Fi 4 + Bluetooth LE 5.0 ESP32-S3 Engineering Sample Stage on a DevKit:

ESP32-S3-Addax-1_V1.0
ESP32-S3 (Beta2) Codename: #MARLIN_9_1B
TimeStamp: 522020

- ESP32-S3 got marketing state : Sample
select left ESP32-S3
you see right one item - ESP32-S3 - and the Marketing Status "Sample" -
select it right - you see then on top new updated Digram which is in the Prerelease V0.3.1 also the Specs -

- The DevKit ESP32-S3-Addax-1_V1.0 is on my Desk and you find pictures now on my Twitter cause the ESP32-S3 was spotted in the wild so no more reason to hidden this news from community.

- Codesamples: the RGB is working well with my Rainbow Test and is online at YT for the processing as 4K show-ing-

- my Starlight shootings for details are online too

- Stickley-S2 has now a big brother -S3 (Beta2) - *soon updated cause it is only engineering sample and preview - no release/final SoC*

- The FreeHeapSize is just in time in this RGB Example : 8766283 cause it has 8 MB PSRAM on Board, also 8 MB Flash

- ESP32-S3 (Beta2) got unofficialy Arduino support from me in Sloeber like the ESP32-S2


now i will be killed for this
no risc no fun

btw risc
RISC-V ESP32-C3 - there comes an other post perhabs later - but not now
there are few infos i want share too - i will update soon'lish the C3 post
but for now i close it cause we have urgent to do with the ESP32-S3 and an here in BBS not Named ESP DevKit
but it is also spotted in the wild - i found it in the espressif github -
a mishap? perhaps - no one has noticed it yet - easter egg? perhaps

best wishes
rudi


EDIT:
Sharing (my own) Pictures
you can share it without any limition but do not change
i added total 4 pics by linking, but linked picture was not show to guest if you not be logged in
I added now one Pictures on the Top of this post by uploading it now
it can be, that you must logged in to can see all pictures here.
please let me know if you can't see pictures if you logged in.

Edit: ( uploaded further 2 Picture only, cause max 3 files allowed for upload )

ESP32-S3-Addax-1_V1.0
Topview

ESP32-S3-Addax-1_V1.0.jpg (633.69 KiB) Viewed 36462 times

ESP32-S3-Addax-1_V1.0
Bottomview

ESP32-S3-Addax-1_V1.0.jpg (563.47 KiB) Viewed 36462 times

Edit: updated S3 Datasheet (Prerelease V0.3) Link

[Vader_Mester]

I'm so glad you made this post! I'm totally excited about this thing!

[Baldhead]

Hi @rudi,

There is a esp32-s3 technical reference manual ?

Thank's.

[Baldhead]

Hi,

It looks like they're not using spi octal bus.

And it looks like both flash memory and external ram memory share the same sqi bus.

They should have made a chip that supported independent sqi bus access to each memory (flash and external ram).

[neggles]

It looks like they're not using spi octal bus.

And it looks like both flash memory and external ram memory share the same sqi bus.

They should have made a chip that supported independent sqi bus access to each memory (flash and external ram).

Obviously we can't be sure about any of this until the final datasheet is released (or at least a public datasheet), but from the datasheet linked here, you're wrong on both counts.

There are four SPI controllers. SPI0 and SPI1 are master-only interfaces, dedicated to flash/RAM use, and it looks like you can use them as independent QSPI interfaces or as a single octSPI interface.

That should mean you can connect a QSPI flash chip to SPI0 + QSPI PSRAM to SPI1 and have dedicated QSPI controllers for both, or use SPI0+1 in octSPI mode, shared between an octSPI flash chip and octSPI PSRAM.

But if that's not enough for you, SPI2 is also octSPI capable, can be a master or a slave, and can also be used to connect flash/RAM! If I'm reading this right, and you desperately need the performance, you should be able to connect an octSPI flash/RAM chip to SPI0+1 in octSPI mode and connect another octSPI flash/RAM chip to SPI2 in octSPI mode at the same time!

You'd even still have SPI3 (QSPI capable master/slave) spare to use with other devices.

I can't imagine a lot of situations where you'd actually need two octSPI flash/RAM interfaces - dedicated QSPI is more than adequate for most things I can think of, and the 2nd octSPI controller would probably be more useful for a high-speed peripheral - but it does indeed appear to be possible, and the chip has support for up to 1GB (!!) of external memory, which is kind of wild.

[Baldhead]

"I can't imagine a lot of situations where you'd actually need two octSPI flash/RAM interfaces - dedicated QSPI is more than adequate for most things I can think of, and the 2nd octSPI controller would probably be more useful for a high-speed peripheral - but it does indeed appear to be possible, and the chip has support for up to 1GB (!!) of external memory, which is kind of wild."

Hi @neggles,

Through the photos they are certainly not using octalspi, unless they divided the high nibble and low nibble for each memory or are using low nibble for both memories(what I highly doubt).
The chips have only 8 pins.
Regarding sqi we cannot infer anything, but i really hope they used an sqi bus for each memory.

I really suggested in an espressif question here on the forum that they put an independent sqi bus for each memory. And i hope that these two sqi bus are ddr and not sdr.

[Baldhead]

I'm not sure, but there are some spi / qspi / octalSpi that share the same dma.

If those spi / qspi / octalSpi that access the external memory are the same as those that interface with some fast device, it will most likely be a problem.

[neggles]

Through the photos they are certainly not using octalspi, unless they divided the high nibble and low nibble for each memory or are using low nibble for both memories(what I highly doubt).
The chips have only 8 pins.
Regarding sqi we cannot infer anything, but i really hope they used an sqi bus for each memory.

I really suggested in an espressif question here on the forum that they put an independent sqi bus for each memory. And i hope that these two sqi bus are ddr and not sdr.

On this particular development board they're not using octal-SPI, but it does appear to be possible. SPI0 and SPI1 are limited to flash/RAM usage only and have fixed pin assignments, so it's probably a fairly safe bet that one of them is connected to flash and the other to RAM (leaving SPI2 and SPI3 free for peripherals).

This is probably going to be the most common configuration, which is what I'd expect to see on a dev board, but that doesn't mean you can't design your own board that has dual octal-SPI memory (or wait for someone else to do it - if it's possible, someone will build it).

I'm not sure, but there are some spi / qspi / octalSpi that share the same dma.

If those spi / qspi / octalSpi that access the external memory are the same as those that interface with some fast device, it will most likely be a problem.

From the "DMA Controller" section on page 22 (emphasis mine);

ESP32-S3 has a general-purpose DMA controller with five independent channels, all used for both transmit and receive directions. These five channels are shared by peripherals with DMA feature, and support dynamic priority.

The DMA controller controls data transfer using linked lists. It allows peripheral-to-memory and memory-to-memory data transfer at a high speed. All channels can access internal and external RAM.

Peripherals on ESP32-S3 with DMA feature are SPI2, SPI3, UHCI0, I2S0, I2S1, LCD/CAM, AES, SHA, and ADC/DAC.

This is new, I think? DMA access to external RAM was not previously possible, as far as I can tell - so it looks like in dual-QSPI mode at least there won't be any DMA contention to worry about, and it looks like the five DMA controllers aren't restricted to any specific peripheral, so that's neat.

All that said, I think you guys might be expecting a bit much of a $2-5 microcontroller module. If you need dual octal-SPI memory with dedicated controllers, and a bunch more peripherals, etc then you should probably be looking at more powerful (ARM-based, probably) chips...

My only real complaint is that the TWAI interface still doesn't support ISO 11898-1:2015 (CAN-FD)

[Baldhead]

Hi @neggles,

I was basing my assumptions on the esp32-s2 chip technical reference manual, but esp32-s3 may have a different dma architecture.

"This is new, I think? DMA access to external RAM was not previously possible, as far as I can tell"
In esp32-s2 thecnical reference manual this is possible too.

Esp32-s2 thecnical reference manual page 174:

"ESP32-S2 has three types of DMA, namely Internal DMA, EDMA and Copy DMA. Internal DMA can only access
internal RAM and is used for data transfer between internal RAM and peripherals. EDMA can access both
internal RAM and external RAM and is used for data transfer between internal RAM, external RAM and
peripherals. Copy DMA can only access internal RAM and is used for data transfer from one location in internal
RAM to another."

Regarding the communication with the flash memory and external ram memory, i would be very happy with a sqi ddr bus for each memory, with independent cache/memory controller for each external memory.

[rudi ;-)]

I'm so glad you made this post! I'm totally excited about this thing!

u're welcome