DEEPSLEEP_RESET

[beg_dk]

Hi

I am currently looking for a way to wakeup esp32 from deep sleep via gpio 13 which should be possible with rtc.

I am using an example from pcbreflux and changed it sligthly.

Code: Select all

#include <stdio.h>
#include <string.h>
#include <stdlib.h>

#include "sdkconfig.h"

#include "esp_deep_sleep.h"

#define GPIO_INPUT_IO_TRIGGER     13  // use pin 13

void app_main() {
	printf("start ESP32\n");

	printf("config IO\n");
	esp_deep_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_AUTO); //!< Keep power domain enabled in deep sleep, if it is needed by one of the wakeup options. Otherwise power it down.
	gpio_pullup_en(GPIO_INPUT_IO_TRIGGER);		// use pullup on GPIO
	gpio_pulldown_dis(GPIO_INPUT_IO_TRIGGER);       // not use pulldown on GPIO

	esp_deep_sleep_enable_ext0_wakeup(GPIO_INPUT_IO_TRIGGER, 1); // Wake if GPIO is high

	printf("deep sleep\n");
	esp_deep_sleep_start();

}

First, I got both a TG0WDT_SYS_RESET and DEEPSLEEP_RESET but after doing a pull from master, I now only get DEEPSLEEP_RESET.

Here is the output

Code: Select all

start ESP32
config IO
deep sleep
I (210) cpu_start: Starting scheduler on APP CPU.
ets Jun  8 2016 00:22:57

rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:8
load:0x3fff0010,len:4124
ho 0 tail 12 room 4
load:0x40078000,len:9228
load:0x40080000,len:252
entry 0x40080034
I (48) boot: ESP-IDF v2.0-rc1-443-g3cad00f-dirty 2nd stage bootloader
I (48) boot: compile time 09:08:45
I (52) boot: Enabling RNG early entropy source...
I (69) boot: SPI Speed      : 40MHz
I (81) boot: SPI Mode       : DIO
I (94) boot: SPI Flash Size : 4MB
I (106) boot: Partition Table:
I (117) boot: ## Label            Usage          Type ST Offset   Length
I (140) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (163) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (187) boot:  2 factory          factory app      00 00 00010000 00100000
I (210) boot: End of partition table
I (223) boot: Disabling RNG early entropy source...
I (240) boot: Loading app partition at offset 00010000
I (831) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512)
I (832) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x078e0 ( 30944) map
I (848) boot: segment 2: paddr=0x000278f0 vaddr=0x3ffc0000 size=0x024bc (  9404) load
I (878) boot: segment 3: paddr=0x00029db4 vaddr=0x40080000 size=0x00400 (  1024) load
I (901) boot: segment 4: paddr=0x0002a1bc vaddr=0x40080400 size=0x17914 ( 96532) load
I (972) boot: segment 5: paddr=0x00041ad8 vaddr=0x400c0000 size=0x00034 (    52)
I (973) boot: segment 6: paddr=0x00041b14 vaddr=0x00000000 size=0x0e4f4 ( 58612)
I (988) boot: segment 7: paddr=0x00050010 vaddr=0x400d0018 size=0x240bc (147644) map
I (1014) cpu_start: Pro cpu up.
I (1026) cpu_start: Starting app cpu, entry point is 0x40080d44
I (0) cpu_start: App cpu up.
I (1059) heap_alloc_caps: Initializing. RAM available for dynamic allocation:
I (1081) heap_alloc_caps: At 3FFAFF10 len 000000F0 (0 KiB): DRAM
I (1101) heap_alloc_caps: At 3FFC5A70 len 0001A590 (105 KiB): DRAM
I (1123) heap_alloc_caps: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
I (1144) heap_alloc_caps: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (1166) heap_alloc_caps: At 40097D14 len 000082EC (32 KiB): IRAM
I (1186) cpu_start: Pro cpu start user code
I (1247) cpu_start: Starting scheduler on PRO CPU.

Does anyone know why that is?

Thanks

[ESP_igrr]

https://github.com/espressif/esp-idf/is ... -291916959

you should set "Extra delay in deep sleep wake stub (in us)" option under "ESP32 specific" menu in menuconfig to some value like 500 (microseconds)

[beg_dk]

Setting "Extra delay in deep sleep wake stub (in us)" option under "ESP32 specific" menu in menuconfig to some value like 500 (microseconds) did not work out.

Also what I find strange is that the original example from pcbreflux works without having to set an extra delay in deep sleep wake stub

Code: Select all

#include <stdio.h>
#include <string.h>
#include <stdlib.h>

#include "sdkconfig.h"

#include "esp_deep_sleep.h"

#define GPIO_INPUT_IO_TRIGGER     0  // There is the Button on GPIO 0

void app_main() {
	printf("start ESP32\n");

	printf("config IO\n");
	esp_deep_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_AUTO); //!< Keep power domain enabled in deep sleep, if it is needed by one of the wakeup options. Otherwise power it down.
	gpio_pullup_en(GPIO_INPUT_IO_TRIGGER);		// use pullup on GPIO
	gpio_pulldown_dis(GPIO_INPUT_IO_TRIGGER);       // not use pulldown on GPIO

	esp_deep_sleep_enable_ext0_wakeup(GPIO_INPUT_IO_TRIGGER, 0); // Wake if GPIO is low

	printf("deep sleep\n");
	esp_deep_sleep_start();

}

Thanks

[ESP_igrr]

So you are getting DEEPSLEEP_RESET now, no TG0WDT reset? If so, that's the correct behavior, am I missing something?

[beg_dk]

Ok, to sum up..

I no longer get TG0WDT, that is good.

But only the example with gpio 0 and setting it to trigger on low works.

It does not work if I use gpio 13 and setting it to trigger on high.

Thanks

[WiFive]

You have pullup enabled instead of pulldown?

[ESP_igrr]

gpio_pullup_en(GPIO_INPUT_IO_TRIGGER); // use pullup on GPIO


I thought this was supposed to test immediate wakeup or something... Maybe you need to set trigger level to 0 if you *don't* want the chip to wake up immediately?

[akdogan]

I spent way too much time on the same issue, and finnally solved it. I think it is a bug in revision-0 chips. I solved it by putting two direct register set commands right after esp_default_wake_deep_sleep() in my stub code.

Code: Select all

 
  esp_default_wake_deep_sleep();
  REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, 4);
  REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, 4);

Make sure to include #include "driver/rtc_io.h". Also make sure that there is enough delay before accessing flash. That can be done in the menuconfig, or in the sub itself. This is another bug in hardware, I think, which is due to the slow flash chip. The wakeup must be as fast as possible.

(I have another problem, I'll ask in another post, and I appreciate any help I can get.)

Best wishes.

[ESP_igrr]

Code: Select all

  REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, 4);
  REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, 4);

Could you explain the reason behind the change? This doesn't look like it fixes any hardware bug, at least none that we know of. Could you describe the difference between behavior you see with and without these lines?

[akdogan]

I honestly am not sure. But, resetting the RTC bias voltage solved the problem, thus I "assumed" a hardware bug, maybe I should have chosen my word more carefully. But, what I am sure is that, after inserting those two lines, spurious watchdog resets disappeared, which used to happen after second wakeup. I basically found the solution after a long chain of educated trial end errors.