What defines SPI Flash/RAM pins?

[tannewt]

What defines the pins that are used for SPI Flash and RAM? I was looking at the WROOM and WROVER ESP32-S2 modules and was surprised to find the flash on IO35-37. The S2 data sheet suggests (section 2.4.2) that pins < IO7 are more commonly used.

I ask because I designed a breakout assuming IO35-37 would be free and able to connect to SPI2 through the IOMUX. I'm implementing CircuitPython on the S2 and would love to use SPI2 primarily. I expected SPI1 to be used for the external flash and ram.

So, what is the setup for the S2 modules and where is it defined? I didn't see it in the kconfig.

Thanks!

[WiFive]

The S2 data sheet suggests (section 2.4.2) that pins < IO7 are more commonly used.

That's not what it means, it is talking about the bit lines of the spi interface not the gpios.

[mythbuster_5]

This is defined in efuse. But I strongly recommend you not do that.