When the RTC reset, 0x10 is issued, what values of GPIO_STRAP_REG are used?
Are the values what was latched when the Enable pin was last toggled and not when the RTC reset issued?
Are there any external pins like the Chip_PU/Enable pin toggled?
What is recommended so the external strap pins can be places in the appropriate mode, in our case spi boot. Since there is no outside indication, i dont know how we can put D0 & D1 in the proper state.
Here is the sequence and you can see the chip is going into download mode
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
flash read err, 1000
ets_main.c 371
ets Jun 8 2016 00:22:57 11:08
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
rst:0x10 (RTCWDT_RTC_RESET),boot:0x3 (DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_REO_V2) 11:10
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