ESP AT how to change to pico-d4 module ?

[Honzik321]

Hi,

what is the correct process to change from wroom-32 to pico-d4 module ? There are different pinout for rx, tx, cts, rts between these modules. The configuration od wroom=32 doesnt work on pico=d4 module.

Thank you,
John

[Honzik321]

Hello,

I have changed to PICO-D4 in Makefile. But no "ready" message after RESET is read on any pin of my ESP32-PICO-KIT_V4.1 module.

There is some warning during make defconfig: "Makefile:29: There is no module_config/module_pico-d4,Using module_config/module_esp32_default"

Could be the problem read from BOOT messages on UART -> TX0 ? If yes, could you help ? I send it below:

ets Jun 8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0018,len:4
load:0x3fff001c,len:6952
load:0x40078000,len:14368
ho 0 tail 12 room 4
load:0x40080400,len:4248
entry 0x400806e0
�[0;32mI (74) boot: Chip Revision: 1�[0m
�[0;32mI (74) boot_comm: chip revision: 1, min. bootloader chip revision: 0�[0m
�[0;32mI (42) boot: ESP-IDF v4.0-174-gf9cb434ee 2nd stage bootloader�[0m
�[0;32mI (42) boot: compile time 16:05:33�[0m
�[0;32mI (42) boot: Enabling RNG early entropy source...�[0m
�[0;32mI (47) boot: SPI Speed : 40MHz�[0m
�[0;32mI (51) boot: SPI Mode : DIO�[0m
�[0;32mI (55) boot: SPI Flash Size : 4MB�[0m
�[0;32mI (59) boot: Partition Table:�[0m
�[0;32mI (63) boot: ## Label Usage Type ST Offset Length�[0m
�[0;32mI (70) boot: 0 phy_init RF data 01 01 0000f000 00001000�[0m
�[0;32mI (78) boot: 1 otadata OTA data 01 00 00010000 00002000�[0m
�[0;32mI (85) boot: 2 nvs WiFi data 01 02 00012000 0000e000�[0m
�[0;32mI (93) boot: 3 at_customize unknown 40 00 00020000 000e0000�[0m
�[0;32mI (100) boot: 4 ota_0 OTA app 00 10 00100000 00180000�[0m
�[0;32mI (108) boot: 5 ota_1 OTA app 00 11 00280000 00180000�[0m
�[0;32mI (115) boot: End of partition table�[0m
�[0;32mI (120) boot_comm: chip revision: 1, min. application chip revision: 0�[0m
�[0;32mI (127) esp_image: segment 0: paddr=0x00100020 vaddr=0x3f400020 size=0x20924 (133412) map�[0m
�[0;32mI (183) esp_image: segment 1: paddr=0x0012094c vaddr=0x3ffbdb60 size=0x03788 ( 14216) load�[0m
�[0;32mI (189) esp_image: segment 2: paddr=0x001240dc vaddr=0x40080000 size=0x00400 ( 1024) load�[0m
�[0;32mI (190) esp_image: segment 3: paddr=0x001244e4 vaddr=0x40080400 size=0x0bb2c ( 47916) load�[0m
�[0;32mI (219) esp_image: segment 4: paddr=0x00130018 vaddr=0x400d0018 size=0xff2fc (1045244) map�[0m
�[0;32mI (590) esp_image: segment 5: paddr=0x0022f31c vaddr=0x4008bf2c size=0x10618 ( 67096) load�[0m
�[0;32mI (618) esp_image: segment 6: paddr=0x0023f93c vaddr=0x400c0000 size=0x00064 ( 100) load�[0m
�[0;32mI (635) boot: Loaded app from partition at offset 0x100000�[0m
�[0;32mI (635) boot: Disabling RNG early entropy source...�[0m
2.0.0 max tx power=78,ret=0