ESP32 Forum

Can I get a little clarity on how the #WP pin is used on the SPI master drivers? The only thing the documentation mentions is the WP idle level, but it doesn't have any description of how the pin toggles when in use (esp. with regards to the command/address/data phases). Some of that can be inferred from SPI flash datasheets, and I can empirically test it somewhat by throwing the scope on the lines, but I'd love to see a more definitive description of when #WP is and is not asserted.

Similar data on the HD pin would also be handy, but that's actually a little easier to guess.

Normally, they don't move (from memory: WP is at the idle level you set, #HD is high). When in quad I/O mode, however, they're used as data lines and will carry data then.

Right, I know about the WP/HD lines in quad mode. I was hoping to abuse at least one line for the #C/D line of an OLED SPI display to automate setting the row address without two separate SPI transactions, but I guess I'll just bite the bullet and live with toggling a GPIO and waiting for the command byte to finish. Can't take care of everything in hardware.

fraveydank wrote:Right, I know about the WP/HD lines in quad mode. I was hoping to abuse at least one line for the #C/D line of an OLED SPI display to automate setting the row address without two separate SPI transactions, but I guess I'll just bite the bullet and live with toggling a GPIO and waiting for the command byte to finish. Can't take care of everything in hardware.

Huh, that's actually a pretty nifty idea... but unfortunately you indeed can't do that. Please do look at the spi-master example, however; I've added a callback to the SPI driver that kicks in just before a new transaction starts, specifically to do things like set the D/C line to the correct value.