ESP32 Forum

The esp32 technical reference manual section 3.2.2 states that PLL_CLK is an internal clock with 320Mhz frequency and section 3.2.3 states:


<<As Figure 6 shows, CPU_CLK is the master clock for both CPU cores. CPU_CLK clock can be as high as 160 MHz when the CPU is in high performance mode. Alternatively, the CPU can run at lower frequencies to reduce power consumption>>

However, all esp32 modules that I got go up to 240Mhz. How is that cpu clock achieved? Is PLL_CLK running at 480Mhz rather than 320?

Yes

yes?

I assume 'yes' means PLL_CLK runs at 480 Mhz?

What about the other clock sources?

Where can I find a version of the technical reference manual that has correct clocking information?

Correct. Only pll clk and CPU clk are affected. Apb clk is still 80mhz.