Met guys in Shenzhen claiming making a 100% synchronous refresh free DRAM
Posted: Sun Sep 15, 2019 11:52 am
http://www.xingmem.com/en/product_xm7a.php
Quite an interesting development, what do you think? Inside the chip, there are multiple banks one of which is refreshed during each clock cycle. When read comes when for the bank being refreshed, its content is restored using ECC during the same clock cycle, and same is true for write. All ECC logic is fabbed on the same die apparently.
Looks to me a way more potent thing than most PSRAM designs.
Quite an interesting development, what do you think? Inside the chip, there are multiple banks one of which is refreshed during each clock cycle. When read comes when for the bank being refreshed, its content is restored using ECC during the same clock cycle, and same is true for write. All ECC logic is fabbed on the same die apparently.
Looks to me a way more potent thing than most PSRAM designs.