SPI boot/pin mux config question

[chrisz]

Can the ESP32 boot off of any SPI interface other than SPI (e.g. HSPI, VSPI)? The reason that I ask is that if not, and maybe I'm missing something here, it doesn't appear that there's a pin config that support SPI boot, SD, and JTAG access.

Using the function 5 values for SD_*, MTDI is shared with SD_DATA2 on the alternate function and MTMS is shared with SD_CLK.

So is the aforementioned config possible (SPI boot, SD, and JTAG simultaneously)?

[ESP_Sprite]

It can boot from HSPI as well, if I recall correctly. Plus, you have the option of remapping pins after boot. I think you can even remap some _before_ boot, by using the efuses, but that's not documented yet.

[WiFive]

It can boot from HSPI as well, if I recall correctly. Plus, you have the option of remapping pins after boot. I think you can even remap some _before_ boot, by using the efuses, but that's not documented yet.

So there are more strapping pins? Are we also going to get some details/quantifications on the effect of gpio matrix routing on high speed signals?

[chrisz]

It can boot from HSPI as well, if I recall correctly. Plus, you have the option of remapping pins after boot. I think you can even remap some _before_ boot, by using the efuses, but that's not documented yet.

I'm hoping for VSPI here -- HSPI gets in the way of JTAG. VSPI doesn't interfere with anything I care about. According to Greg, VSPI should work.

[ESP_Sprite]

It's configurable by efuses. The effect of routing high-speed signals over the GPIO matrix is a latency of 2 clock cycles, iirc. It's somewhere in the techdocs, if memory serves.

[WiFive]

It's configurable by efuses. The effect of routing high-speed signals over the GPIO matrix is a latency of 2 clock cycles, iirc. It's somewhere in the techdocs, if memory serves.

Ah OK so program the efuse over serial first. I'm not sure if the docs specify the clock cycles, so thanks.