Debugging a WROOM-32 with FT232R

[ESP_Sprite]

Strange... there is a good hint that your hardware is probably working, at least up to a point: the entire bit before the gdb connection is expected and good. Not sure what fails after that, though... you could possibly try lowering your adapter_khz, sometimes that makes a difference.

[bibble235]

So this is the complete script as I understand it. This obviously could have a bug in it but is here to maybe help someone work through the issue. May have to raise a bug (Suspect same audience)

Below is
*config for openocd
*initial output
*output post starting debugger

This is running on
*esp-wroom-32
*ft232r
*unbuntu 21.04

Code: Select all

interface ft232r
# ft232r_restore_serial 0x15

ft232r_tdi_num TXD
ft232r_tck_num DTR
ft232r_tdo_num RXD
ft232r_tms_num CTS
# trst/srst are not used but must have different values than above
ft232r_trst_num DCD
ft232r_srst_num RI

reset_config none

adapter_khz 20000


set ESP32_FLASH_VOLTAGE 3.3

# ESP_COMMON.CFG

set _FLASH_SIZE "auto"
puts "==== FLASH_SIZE $_FLASH_SIZE"

set _SEMIHOST_BASEDIR "."
puts "==== SEMIHOST_BASEDIR $_SEMIHOST_BASEDIR"


###
### configure_esp_workarea
###
proc configure_esp_workarea { TGT CODE_ADDR CODE_SZ DATA_ADDR DATA_SZ } {
        #WARNING: be careful when selecting working ares for code and data, they should not overlap due to ESP32 physical memory mappings
        $TGT configure -work-area-phys $CODE_ADDR -work-area-virt $CODE_ADDR -work-area-size $CODE_SZ -work-area-backup 1
        # since ESP32 cannot use single address space for code and data we need additional working area to keep data
        $TGT configure -alt-work-area-phys $DATA_ADDR -alt-work-area-virt $DATA_ADDR -alt-work-area-size $DATA_SZ -alt-work-area-backup 1
}


###
### configure_esp_workarea
###
proc configure_esp_flash_bank { TGT DRV SIZE } {
        set _SIZE SIZE
	# special value for flash driver
        set _SIZE 0

        # whole flash for programming purposes
        # TODO: remove it when support for GDB's 'load' comand is implemented
        flash bank $TGT.flash $DRV 0x0 $_SIZE 0 0 $TGT
        # So define mapped flash regions as separate flashes
        # OOCD creates memory map using registered flash banks
        flash bank $TGT.irom $DRV 0x0 0 0 0 $TGT
        flash bank $TGT.drom $DRV 0x0 0 0 0 $TGT
}

# ESP32.cfg 

# The ESP32 only supports JTAG.
# transport select jtag

# Target specific registers
set EFUSE_BLK0_RDATA1_REG 0x3ff5A004

set _CHIPNAME esp32
puts "==== CHIPNAME $_CHIPNAME"

set _CPUTAPID 0x120034e5
puts "==== CPUTAPID $_CPUTAPID"

set _ONLYCPU 3
puts "==== ONLYCPU $_ONLYCPU"

set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE
puts "==== FLASH_VOLTAGE $_FLASH_VOLTAGE"

set _CPU0NAME cpu0
set _CPU1NAME cpu1
set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME

set _RTOS "FreeRTOS"
puts "==== RTOS $_RTOS"


jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID

target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0 -rtos $_RTOS
configure_esp_workarea $_TARGETNAME_0 0x40090000 0x3400 0x3FFC0000 0x10000
configure_esp_flash_bank $_TARGETNAME_0 $_CHIPNAME $_FLASH_SIZE

# APP-CPU
target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1 -rtos $_RTOS
configure_esp_flash_bank $_TARGETNAME_1 $_CHIPNAME $_FLASH_SIZE
target smp $_TARGETNAME_0 $_TARGETNAME_1


$_TARGETNAME_0 esp32 flashbootstrap $_FLASH_VOLTAGE
$_TARGETNAME_0 xtensa maskisr on
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
$_TARGETNAME_0 esp semihost_basedir $_SEMIHOST_BASEDIR

$_TARGETNAME_1 configure -event gdb-attach {
    $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
    # necessary to auto-probe flash bank when GDB is connected
    halt
}

The openocd output at start up (no debug to shorten the pose)

Code: Select all

./openocd     -f ../share/openocd/scripts/interface/iain.cfg 
Open On-Chip Debugger  v0.10.0-esp32-20210401 (2021-04-01-15:45)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
==== FLASH_SIZE auto
==== SEMIHOST_BASEDIR .
==== CHIPNAME esp32
==== CPUTAPID 0x120034e5
==== ONLYCPU 3
==== FLASH_VOLTAGE 3.3
==== RTOS FreeRTOS
==================================== Scooby doo 1
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 3000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : Listening on port 3333 for gdb connections

The openocd output post start up

Code: Select all

Info : 552 9673 server.c:100 add_connection(): accepting 'gdb' connection on tcp/3333
Debug: 553 9673 breakpoints.c:358 breakpoint_clear_target_internal(): Delete all breakpoints for target: esp32.cpu0
Debug: 554 9673 breakpoints.c:358 breakpoint_clear_target_internal(): Delete all breakpoints for target: esp32.cpu1
Debug: 555 9673 breakpoints.c:552 watchpoint_clear_target(): Delete all watchpoints for target: esp32.cpu0
Debug: 556 9673 FreeRTOS.c:1174 FreeRTOS_clean(): FreeRTOS_clean
Debug: 557 9673 FreeRTOS.c:694 FreeRTOS_update_threads(): FreeRTOS_update_threads
Warn : 558 9673 FreeRTOS.c:702 FreeRTOS_update_threads(): No symbols for FreeRTOS!
Debug: 559 9673 target.c:1636 target_call_event_callbacks(): target event 19 (gdb-attach) for core esp32.cpu0
Debug: 560 9673 target.c:4637 target_handle_event(): target(0): esp32.cpu0 (esp32) event: 19 (gdb-attach) action: halt
Debug: 561 9673 command.c:143 script_debug(): command - halt halt
Debug: 563 9715 target.c:3133 handle_halt_command(): -
Debug: 564 9715 xtensa.c:1133 xtensa_halt(): xtensa_halt, target: esp32.cpu0
Debug: 565 9721 xtensa.c:1145 xtensa_halt(): esp32.cpu0: Core status 0x80000000
Debug: 566 9743 xtensa.c:890 xtensa_fetch_all_regs(): esp32.cpu0: start
Debug: 567 10350 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (80318411)
Debug: 568 11162 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (80008000)
Debug: 569 11217 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (80008000)
Debug: 570 11217 xtensa.c:1851 xtensa_poll(): esp32.cpu0: Target halted, pc=0x400E4C76, debug_reason=00000000, oldstate=00000001
Debug: 571 11217 xtensa.c:1856 xtensa_poll(): esp32.cpu0: Halt reason=0x00000000, exc_cause=0, dsr=0x80008000
Info : 572 11217 xtensa.c:1859 xtensa_poll(): esp32.cpu0: Target halted, PC=0x400E4C76, debug_reason=00000000
Debug: 573 11225 esp_xtensa_smp.c:229 esp_xtensa_smp_update_halt_gdb(): GDB target 'esp32.cpu0'
Info : 574 11225 esp_xtensa_smp.c:234 esp_xtensa_smp_update_halt_gdb(): Set GDB target to 'esp32.cpu0'
Debug: 575 11225 esp_xtensa_smp.c:243 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu0'
Debug: 576 11225 esp_xtensa_smp.c:243 esp_xtensa_smp_update_halt_gdb(): Check target 'esp32.cpu1'
Debug: 577 11225 esp_xtensa_smp.c:257 esp_xtensa_smp_update_halt_gdb(): Poll target 'esp32.cpu1'
Info : 578 11230 xtensa.c:1797 xtensa_poll(): esp32.cpu1: Debug controller was reset.
Debug: 579 11230 xtensa.c:726 xtensa_smpbreak_write(): esp32.cpu1: write smpbreak set=0x30000 clear=0x600000
Info : 580 11240 xtensa.c:1803 xtensa_poll(): esp32.cpu1: Core was reset.
Debug: 581 11252 esp_xtensa.c:212 esp_xtensa_poll(): esp32.cpu1: Clear debug stubs info
Debug: 582 11256 esp_xtensa_smp.c:286 esp_xtensa_smp_update_halt_gdb(): exit
Debug: 583 11256 target.c:1636 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32.cpu0
Debug: 584 11256 esp32.c:521 esp32_handle_target_event(): 0
Debug: 585 11256 esp_xtensa_smp.c:572 esp_xtensa_smp_handle_target_event(): 0
Debug: 586 11256 esp_xtensa.c:109 esp_xtensa_handle_target_event(): 0
Debug: 587 11256 xtensa.c:2438 xtensa_handle_target_event(): 0
Debug: 588 11256 target.c:1636 target_call_event_callbacks(): target event 1 (halted) for core esp32.cpu0
Debug: 589 11256 esp32.c:521 esp32_handle_target_event(): 1
Debug: 590 11256 esp_xtensa_smp.c:572 esp_xtensa_smp_handle_target_event(): 1
Debug: 591 11256 esp_xtensa.c:109 esp_xtensa_handle_target_event(): 1
Debug: 592 11256 xtensa.c:2438 xtensa_handle_target_event(): 1
Debug: 593 11256 esp_xtensa.c:248 esp_xtensa_dbgstubs_info_update(): esp32.cpu0: Read debug stubs info 0 / 0
Debug: 594 11256 target.c:2537 target_write_u32(): address: 0x3ff5f064, value: 0x50d83aa1
Debug: 595 11275 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8000C000)
Debug: 596 11275 target.c:2537 target_write_u32(): address: 0x3ff5f048, value: 0x00000000
Debug: 597 11294 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8000C000)
Debug: 598 11294 target.c:2537 target_write_u32(): address: 0x3ff60064, value: 0x50d83aa1
Debug: 599 11313 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8000C000)
Debug: 600 11313 target.c:2537 target_write_u32(): address: 0x3ff60048, value: 0x00000000
Debug: 601 11332 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8000C000)
Debug: 602 11332 target.c:2537 target_write_u32(): address: 0x3ff480a4, value: 0x50d83aa1
Debug: 603 11351 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8000C000)
Debug: 604 11351 target.c:2537 target_write_u32(): address: 0x3ff4808c, value: 0x00000000
Debug: 605 11370 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8000C000)
Debug: 606 11370 esp32.c:521 esp32_handle_target_event(): 19
Debug: 607 11370 esp_xtensa_smp.c:572 esp_xtensa_smp_handle_target_event(): 19
Debug: 608 11370 esp_xtensa.c:109 esp_xtensa_handle_target_event(): 19
Debug: 609 11370 xtensa.c:2438 xtensa_handle_target_event(): 19
Debug: 610 11370 esp_xtensa.c:828 esp_xtensa_probe(): Flash size = 0 KB @ 0x00000000 'esp32.cpu0' - 'halted'
Debug: 611 11370 esp_xtensa.c:212 esp_xtensa_flasher_image_init(): base=00000000 set=0
Debug: 612 11370 xtensa.c:726 xtensa_smpbreak_write(): esp32.cpu0: write smpbreak set=0x0 clear=0x630000
Debug: 613 11380 xtensa.c:744 xtensa_smpbreak_set(): esp32.cpu0: set smpbreak=0, state=2
Debug: 614 11380 xtensa_algorithm.c:597 xtensa_run_do(): Set arg[0] = 5
Debug: 615 11380 xtensa_algorithm.c:609 xtensa_run_do(): Set arg[1] = -1
Debug: 616 11380 xtensa_algorithm.c:609 xtensa_run_do(): Set arg[2] = 0
Debug: 617 11380 xtensa_algorithm.c:108 xtensa_stub_load(): stub: base 0x0, start 0x40091624, 2 sections
Debug: 618 11380 xtensa_algorithm.c:115 xtensa_stub_load(): addr 0x00000000, sz 7187, flags 1
Debug: 619 11380 target.c:1835 alloc_working_area_try_do(): MMU disabled, using physical address for working memory 0x40090000
Debug: 620 11380 target.c:1889 alloc_working_area_try_do(): allocated new working area of 7188 bytes at address 0x40090000
Debug: 621 22196 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8000C000)
Debug: 622 22196 target.c:1751 print_wa_layout(): b* 0x40090000-0x40091c13 (7188 bytes)
Debug: 623 22196 target.c:1751 print_wa_layout():    0x40091c14-0x400933ff (6124 bytes)
Debug: 624 22196 target.c:2236 target_write_buffer(): writing buffer of 512 byte at 0x40090000
Debug: 625 22980 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8000C000)
Debug: 626 22980 target.c:2236 target_write_buffer(): writing buffer of 512 by

[bibble235]

A new question and an update.
I see in the header for ft232r.c it has the following.

Question

Code: Select all

#define FT232R_BIT_COUNT 8
static char *ft232r_bit_name_array[FT232R_BIT_COUNT] = {
        "TXD", /* 0: pin 1  TCK output */
        "RXD", /* 1: pin 5  TDI output */
        "RTS", /* 2: pin 3  TDO input */
        "CTS", /* 3: pin 11 TMS output */
        "DTR", /* 4: pin 2  /TRST output */
        "DSR", /* 5: pin 9  unused */
        "DCD", /* 6: pin 10 /SYSRST output */
        "RI"   /* 7: pin 6  unused */
};

static int tck_gpio; /* initialized to 0 by default */
static int tdi_gpio = 1;
static int tdo_gpio = 2;
static int tms_gpio = 3;
static int ntrst_gpio = 4;
static int nsysrst_gpio = 6;

Usually I have my board set up like shown in
https://docs.espressif.com/projects/esp ... -jtag.html
MTDO / GPIO15 - TDO
MTDI / GPIO12 - TDI
MTCK / GPIO13 - TCK
MTMS / GPIO14 - TMS
GND - GND

And doing this results in the output.

Code: Select all

Info : 518 28 core.c:1027 jtag_examine_chain_display(): JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : 519 28 core.c:1027 jtag_examine_chain_display(): JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)

But looking at the header file it says GPIO 0-6. When I use this I do not see the JTAG messages but instead errors which I am taking to mean it does not work configured this way.

So my question is more around the ntrst_gpio, nsysrst_gpio which are not mentioned in the espressif link only tdo, tms, tdi, and tck.

Progress
I have raised a bug with the ocd espressif people https://github.com/espressif/openocd-esp32/issues/157
They have been responsive but no been able to help with a positive outcome. They have said that the log I provided looks like it is working. Last part shown. However it hangs on the GDB side with no prompt ie. no (gdb)

Code: Select all

Debug: 2080 174620 command.c:143 script_debug(): command - esp32.cpu1 esp32.cpu1 was_examined
Debug: 2081 174620 command.c:143 script_debug(): command - esp32.cpu1 esp32.cpu1 arp_waitstate halted 1000
Debug: 2082 174642 command.c:143 script_debug(): command - esp32.cpu1 esp32.cpu1 curstate
Debug: 2083 174642 command.c:143 script_debug(): command - esp32.cpu0 esp32.cpu0 invoke-event reset-end
Debug: 2084 174642 command.c:143 script_debug(): command - esp32.cpu1 esp32.cpu1 invoke-event reset-end
Debug: 2085 174729 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$OK#9a'
Debug: 2086 174729 gdb_server.c:3358 gdb_input_inner(): received packet: 'g'
Debug: 2087 174729 xtensa.c:1106 xtensa_get_gdb_reg_list(): reg_class=1, num_regs=105
Debug: 2088 174729 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$00040040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000004004096fec51c1f00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000#ae'
Debug: 2089 174731 gdb_server.c:3358 gdb_input_inner(): received packet: 'm40000400,4'
Debug: 2090 174731 gdb_server.c:1451 gdb_read_memory_packet(): addr: 0x0000000040000400, len: 0x00000004
Debug: 2091 174731 target.c:2300 target_read_buffer(): reading buffer of 4 byte at 0x40000400
Debug: 2092 174750 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8080CC11)
Debug: 2093 174750 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$06130000#8a'
Debug: 2094 174750 gdb_server.c:3358 gdb_input_inner(): received packet: 'm400d2b27,2'
Debug: 2095 174750 gdb_server.c:1451 gdb_read_memory_packet(): addr: 0x00000000400d2b27, len: 0x00000002
Debug: 2096 174750 target.c:2300 target_read_buffer(): reading buffer of 2 byte at 0x400d2b27
Debug: 2097 174775 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8080CC11)
Debug: 2098 174775 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$baad#88'
Debug: 2099 174775 gdb_server.c:3358 gdb_input_inner(): received packet: 'Z1,400d2b27,2'
Debug: 2100 174775 gdb_server.c:1650 gdb_breakpoint_watchpoint_packet(): [esp32.cpu0]
Debug: 2101 174775 xtensa.c:1978 xtensa_breakpoint_add(): esp32.cpu0: placed HW breakpoint @ 0x400d2b27
Debug: 2102 174775 breakpoints.c:106 breakpoint_add_internal(): [0] added hardware breakpoint at 0x400d2b27 of length 0x00000002, (BPID: 0)
Debug: 2103 174775 xtensa.c:1978 xtensa_breakpoint_add(): esp32.cpu1: placed HW breakpoint @ 0x400d2b27
Debug: 2104 174775 breakpoints.c:106 breakpoint_add_internal(): [1] added hardware breakpoint at 0x400d2b27 of length 0x00000002, (BPID: 1)
Debug: 2105 174775 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$OK#9a'
Debug: 2106 174775 gdb_server.c:3358 gdb_input_inner(): received packet: 'vCont?'
Debug: 2107 174775 gdb_server.c:402 gdb_put_packet_inner(): sending packet '$vCont;c;C;s;S#62'
Debug: 2108 174775 gdb_server.c:3358 gdb_input_inner(): received packet: 'vCont;c'
Debug: 2109 174775 gdb_server.c:2808 gdb_handle_vcont_packet(): target esp32.cpu0 continue
Debug: 2110 174775 target.c:1636 target_call_event_callbacks(): target event 3 (resume-start) for core esp32.cpu0
Debug: 2111 174775 esp32.c:521 esp32_handle_target_event(): 3
Debug: 2112 174775 esp_xtensa_smp.c:572 esp_xtensa_smp_handle_target_event(): 3
Debug: 2113 174775 esp_xtensa.c:109 esp_xtensa_handle_target_event(): 3
Debug: 2114 174775 xtensa.c:2438 xtensa_handle_target_event(): 3
Debug: 2115 174775 esp_xtensa_smp.c:342 esp_xtensa_smp_resume(): esp32.cpu0: smp_break=0x30000
Debug: 2116 174775 xtensa.c:726 xtensa_smpbreak_write(): esp32.cpu0: write smpbreak set=0x0 clear=0x630000
Debug: 2117 174785 xtensa.c:744 xtensa_smpbreak_set(): esp32.cpu0: set smpbreak=0, state=2
Debug: 2118 174785 xtensa.c:1180 xtensa_prepare_resume(): esp32.cpu0: current=1 address=0x00000000, handle_breakpoints=0, debug_execution=0)
Debug: 2119 174785 xtensa.c:512 xtensa_write_dirty_registers(): esp32.cpu0: start
Debug: 2120 174785 xtensa.c:526 xtensa_write_dirty_registers(): esp32.cpu0: Writing back reg ibreakenable val 00000001
Debug: 2121 174785 xtensa.c:526 xtensa_write_dirty_registers(): esp32.cpu0: Writing back reg ibreaka0 val 400D2B27
Debug: 2122 174785 xtensa.c:648 xtensa_queue_write_dirty_user_regs_u32(): esp32.cpu0: start
Debug: 2123 174785 xtensa.c:591 xtensa_write_dirty_registers(): esp32.cpu0: Writing back reg a3 value 00000000, num =4
Debug: 2124 174828 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8080CC11)
Debug: 2125 174828 xtensa.c:726 xtensa_smpbreak_write(): esp32.cpu0: write smpbreak set=0x30000 clear=0x600000
Debug: 2126 174838 xtensa.c:744 xtensa_smpbreak_set(): esp32.cpu0: set smpbreak=30000, state=2
Debug: 2127 174838 esp_xtensa_smp.c:313 esp_xtensa_smp_resume_cores(): esp32.cpu0
Debug: 2128 174838 esp_xtensa_smp.c:342 esp_xtensa_smp_resume(): esp32.cpu1: smp_break=0x30000
Debug: 2129 174838 xtensa.c:726 xtensa_smpbreak_write(): esp32.cpu1: write smpbreak set=0x0 clear=0x630000
Debug: 2130 174848 xtensa.c:744 xtensa_smpbreak_set(): esp32.cpu1: set smpbreak=0, state=2
Debug: 2131 174848 xtensa.c:1180 xtensa_prepare_resume(): esp32.cpu1: current=1 address=0x00000000, handle_breakpoints=0, debug_execution=0)
Debug: 2132 174848 xtensa.c:512 xtensa_write_dirty_registers(): esp32.cpu1: start
Debug: 2133 174848 xtensa.c:526 xtensa_write_dirty_registers(): esp32.cpu1: Writing back reg ibreakenable val 00000001
Debug: 2134 174848 xtensa.c:526 xtensa_write_dirty_registers(): esp32.cpu1: Writing back reg ibreaka0 val 400D2B27
Debug: 2135 174848 xtensa.c:648 xtensa_queue_write_dirty_user_regs_u32(): esp32.cpu1: start
Debug: 2136 174848 xtensa.c:591 xtensa_write_dirty_registers(): esp32.cpu1: Writing back reg a3 value 00000000, num =4
Debug: 2137 174891 xtensa.c:788 xtensa_core_status_check(): esp32.cpu1: DSR (8080CC11)
Debug: 2138 174891 xtensa.c:726 xtensa_smpbreak_write(): esp32.cpu1: write smpbreak set=0x30000 clear=0x600000
Debug: 2139 174901 xtensa.c:744 xtensa_smpbreak_set(): esp32.cpu1: set smpbreak=30000, state=2
Debug: 2140 174901 xtensa.c:1233 xtensa_do_resume(): esp32.cpu1: start
Debug: 2141 174911 xtensa.c:788 xtensa_core_status_check(): esp32.cpu1: DSR (8080CC01)
Debug: 2142 174911 target.c:1636 target_call_event_callbacks(): target event 2 (resumed) for core esp32.cpu1
Debug: 2143 174911 esp32.c:521 esp32_handle_target_event(): 2
Debug: 2144 174911 esp_xtensa_smp.c:572 esp_xtensa_smp_handle_target_event(): 2
Debug: 2145 174911 esp_xtensa.c:109 esp_xtensa_handle_target_event(): 2
Debug: 2146 174911 xtensa.c:2438 xtensa_handle_target_event(): 2
Debug: 2147 174911 xtensa.c:1233 xtensa_do_resume(): esp32.cpu0: start
Debug: 2148 174921 xtensa.c:788 xtensa_core_status_check(): esp32.cpu0: DSR (8080CC01)
Debug: 2149 174921 target.c:1636 target_call_event_callbacks(): target event 2 (resumed) for core esp32.cpu0
Debug: 2150 174921 esp32.c:521 esp32_handle_target_event(): 2
Debug: 2151 174921 esp_xtensa_smp.c:572 esp_xtensa_smp_handle_target_event(): 2
Debug: 2152 174921 esp_xtensa.c:109 esp_xtensa_handle_target_event(): 2
Debug: 2153 174921 xtensa.c:2438 xtensa_handle_target_event(): 2
Debug: 2154 174921 target.c:1636 target_call_event_callbacks(): target event 4 (resume-end) for core esp32.cpu0
Debug: 2155 174921 esp32.c:521 esp32_handle_target_event(): 4
Debug: 2156 174921 esp_xtensa_smp.c:572 esp_xtensa_smp_handle_target_event(): 4
Debug: 2157 174921 esp_xtensa.c:109 esp_xtensa_handle_target_event(): 4
Debug: 2158 174921 xtensa.c:2438 xtensa_handle_target_event(): 4
Debug: 2159 174921 target.c:1636 target_call_event_callbacks(): target event 5 (gdb-start) for core esp32.cpu0
Debug: 2160 174921 esp32.c:521 esp32_handle_target_event(): 5
Debug: 2161 174921 esp_xtensa_smp.c:572 esp_xtensa_smp_handle_target_event(): 5
Debug: 2162 174921 esp_xtensa.c:109 esp_xtensa_handle_target_event(): 5
Debug: 2163 174921 xtensa.c:2438 xtensa_handle_target_event(): 5

They say a picture says a thousand words so.
https://www.bibble.co.nz/mediawiki/inde ... FT232R.png
The rest of my progress can be found on https://www.bibble.co.nz/mediawiki/index.php/ESP32