SPI DMA in ESP32-S2-WROOM

[srikanth r]

hi

now we are implemented SPI poling in ESP32-S2-WROOM module. But now I need to implement SPI DMA for Transmit and receive .
is ESP32-S2-WROOM module supports SPI DMA ?
actually we searched in github, I find SPI DMA stack but in that no DMA related functions.

thank you
srikanth

[ESP_Sprite]

Given that you're using the ESP-IDF SPI driver and assign a DMA channel to the host driver when initializing it, you're already using DMA. The driver will use DMA for data transfers automatically.

[srikanth r]

thanks for reply.
Actually we are using the code which is present in the link.
link: https://github.com/hideakitai/ESP32DMASPI
In example i am not seen any interrupt routine for checking Transmit complete and Receive Complete. please let me know if any other examples are there for SPI DMA implementation.


thanks in advance
srikanth

[PeterR]

Keep in mind that DMA can be counter productive for small transfers. One of my SPI channels is a cheap MPC2515 and that is a very chatty device with between 3 and 8 byte transfers. Latency & setup really kill that through put. On the short transfers I measured that no DMA was faster. Basically the SPI FIFO can handle it, you only get the ISR on CS, you don't get hit by SPI full. DMA adds a setup time to the transaction & if not needed then why spend time configuring those register? Clearly longer transfers (which bust the SPI FIFO) would benefit.

[denial]

i'm new to the community and esp32 can i get a simple spi loopback example code for esp32

[svenbieg]

I think DMA is a misunderstanding. Sure, both CPUs have DMA, my PC has an extra DMA-chip onboard. SPI is just a protocol, no hardware. That's a big advantage of the RISC-architecture, there is no need for a DMA-chip. Espressif should remove this expression from their memory-model page.

[ESP_Sprite]

I think DMA is a misunderstanding. Sure, both CPUs have DMA, my PC has an extra DMA-chip onboard. SPI is just a protocol, no hardware. That's a big advantage of the RISC-architecture, there is no need for a DMA-chip. Espressif should remove this expression from their memory-model page.

Do you have sources for 1. Espressif states there is a 'dma chip' in the memory model, and 2. there's no need for a 'dma chip' in a RISC architecture?

[svenbieg]

Do you have sources for 1. Espressif states there is a 'dma chip' in the memory model, and 2. there's no need for a 'dma chip' in a RISC architecture?

1. I couldn't find a dma-controller in the hardware-diagram. The flash-chip itself would have to access memory directly to have DMA.

2. RISC means Reduced Instruction Set Computer. You have multiple cheap CPUs that can do all the tasks. A DMA-controller was necessary in the past when there only was one CPU.

DMA can not be done by software.

[ESP_Sprite]

1. I couldn't find a dma-controller in the hardware-diagram. The flash-chip itself would have to access memory directly to have DMA.

This is because the ESP32 has it inside each peripheral, in the same way as bus mastering on PCI/PCIE does not need a separate DMA controller. (For that matter, 'my PC has an extra DMA-chip onboard' is technically true but only because it needs to be compatible with the very first PC/XT. Any DMA access in modern peripherals happens with the peripheral taking the role of bus master.) Note that our later chips (ESP32C3, ESP32S3) are hybrids: while there's a centralized GDMA block for most peripherals, some peripherals (USB, SDMMC host, ...) still have their own bus master DMA capabilities rather than using that.

2. RISC means Reduced Instruction Set Computer. You have multiple cheap CPUs that can do all the tasks. A DMA-controller was necessary in the past when there only was one CPU.

I agree with the first part. I don't understand how RISC leads to using multiple CPUs, however.

DMA can not be done by software.

This is true. You either need separate DMA hardware, or bus master capabilities in each peripheral. (Or a combination.)