Compilation of RISC-V .c file results in errors

[nvtby_espf]

Hi!
I've a problem with compilation of .c file for ESP32-S2 for ULP-RISC-V. I suppose build system doesn't treat .c file as expected. Here's excerpt from the log:

Code: Select all

>idf.py build
...
[4/385] Performing build step for 'ulp_main'
FAILED: esp-idf/main/ulp_main-prefix/src/ulp_main-stamp/ulp_main-build ... riscv-single/build/esp-idf/main/ulp_main --target build"
[1/6] Generating x_inc.ulp.S
[2/6] Building ASM object CMakeFiles/ulp_main.dir/x_inc.ulp.S.obj
FAILED: CMakeFiles/ulp_main.dir/x_inc.ulp.S.obj
esp32s2ulp-elf-as ...  -o CMakeFiles/ulp_main.dir/x_inc.ulp.S.obj -c x_inc.ulp.S
x_inc.ulp.S: Assembler messages:
x_inc.ulp.S:1: Error: syntax error. Input text was typedef.
x_inc.ulp.S:1: Error:
x_inc.ulp.S:2: Error: syntax error. Input text was typedef.
x_inc.ulp.S:2: Error:
...
x_inc.ulp.S:67: Error:
x_inc.ulp.S:68: Error: syntax error. Input text was }.
x_inc.ulp.S:68: Error:
ninja: build stopped: subcommand failed.
[6/385] Building C object esp-idf/app_update/CMakeFiles/__idf_app_update.dir/esp_app_desc.c.obj
ninja: build stopped: subcommand failed.
ninja failed with exit code 1

The RISC-V file "main/ulp/x_inc.c" is pretty simple:

Code: Select all

#include <stdint.h>
volatile unsigned int edge_count;
int main (void) 
{
    edge_count += 33;
    return 0;
}

The file in question "riscv-single/build/esp-idf/main/ulp_main/x_inc.ulp.S" looks like this:

Code: Select all

typedef signed char __int8_t;
typedef unsigned char __uint8_t;
...
       
typedef __int8_t int8_t ;
typedef __uint8_t uint8_t ;
...
  typedef long long unsigned int uint_fast64_t;
volatile unsigned int edge_count;
int main (void)
{
    edge_count += 33;
    return 0;
}

From my point it looks like misconfiguration of ESP-IDF but I have no idea what. I employ version 4.2 on Windows 10. Here's what has been installed:

Code: Select all

>idf_tools.py list
* xtensa-esp32-elf: Toolchain for Xtensa (ESP32) based on GCC
  - esp-2020r3-8.4.0 (recommended, installed)
* xtensa-esp32s2-elf: Toolchain for Xtensa (ESP32-S2) based on GCC
  - esp-2020r3-8.4.0 (recommended, installed)
* esp32ulp-elf: Toolchain for ESP32 ULP coprocessor
  - 2.28.51-esp-20191205 (recommended, installed)
* esp32s2ulp-elf: Toolchain for ESP32-S2 ULP coprocessor
  - 2.28.51-esp-20191205 (recommended, installed)
* cmake: CMake build system
  - 3.16.4 (recommended, installed)
* openocd-esp32: OpenOCD for ESP32
  - v0.10.0-esp32-20200709 (recommended, installed)
* ninja: Ninja build system
  - 1.10.0 (recommended, installed)
* idf-exe: IDF wrapper tool for Windows
  - 1.0.1 (recommended, installed)
* ccache: Ccache (compiler cache)
  - 3.7 (recommended, installed)
* dfu-util: dfu-util (Device Firmware Upgrade Utilities)
  - 0.9 (recommended, installed)

From a sample on the forum for Kaluga board (https://github.com/Ebiroll/esp32s2_kalu ... ple_main.c) everything is fine. Some people recommend installing toolchain "riscv-none-embed-gcc" but this information doesn't help. Also, include files in working examples refer to "esp32s2/ulp_riscv.h" but I can't find such file in the installation "esp-idf/components/...". And, the doc hints to set option "CONFIG_ESP32S2_ULP_COPROC_RISCV=y" but there's no such option in menuconfig. Manual setting of it in "sdkconfig.defaults" has no effect.

The main question is: Is RISC-V supported in version 4.2 or after?
Does it require extra installation efforts beyond default setup?
Does it needs another commands to build?

Please help. Any idea matters.
Thank you

[ESP_Angus]

Hi nvtby,

Sorry for all the trouble you've had with this.

There are 3 things going on here:

1) ESP-IDF v4.2 doesn't support the RISC-V ULP in ESP32-S2. This support will be added in the v4.3 release, so at present your best options are to git checkout either "v4.3-beta1" or "master" branch and build from there.

2) In the case of your project using ESP-IDF v4.2, the "FSM ULP" toolchain is being used. The ESP32-S2 has two ULPs: the very simple FSM ULP (almost the same as ESP32 ULP), and the RISC-V ULP. FSM ULP only supports assembly, not C code.

3) The build system will always build a .S file as assembly code, not as C code.

After updating to a newer version, you can read more about writing code for the RISC-V ULP here:
https://docs.espressif.com/projects/esp ... isc-v.html

and/or by following this example:
https://github.com/espressif/esp-idf/tr ... /ulp_riscv

EDIT: Updated reply, as original reply missed some information in the post.

[nvtby_espf]

Thank you, ESP_Angus! Things got clear.