What would you like to see in The Next Chip?

[PeterR]

Interesting use/case. An off grid mesh agricultural sensor, sounds fun!

[burckaan]

I believe support for WiFi 6; 802.11 ax is paramount for every IoT device of the future, efficient WiFi connection provided by WiFi 6 allows efficient connection of many IoT clients to a single access point.

[chegewara]

1) USB high speed
2) BLE 5.1 or 5.2

[tvoneicken]

RPi PIO peripheral

[ESP_Sprite]

RPi PIO peripheral

On a personal note: Not gonna lie, I'm drooling all over that thing as well.

[tvoneicken]

RPi PIO peripheral

On a personal note: Not gonna lie, I'm drooling all over that thing as well.

One thing I'm really missing in that PIO thing is the ability to do a table lookup (i.e. random memory access) to do things like color table lookup when sending a framebuffer to a display... Lots of other transformations one could do on the fly with a table lookup...

[Miraculix]

MVIO like in the AVR128DB32. E.g. to use it as a level shifter.

[ihouses]

Hi,

My feedback:

RTC 'identical' to DS3231: What functionality are you missing at the moment?

Add a vdd domain only for the RTC. So is possible to connect a battery or supercap in the same way than in the DS3231.

High speed analog comparators as in order microcontrollers to be able to implement feedback loop of BUCK converters and add current limit in each pulse.

A small configurable logic (similar to the 8-bit microchip) to be able to implement basic glue logic in the same microcontroller.

And of course... more brute speed.

[routeur01]

Hi!
it's would be very interesting to integrate into the ESP32 a little FPGA. For instance, we could integrate directly into the FPGA all I2C peripheral we need. It would consume less power than the ULP co processor. Maybe it could replace the ULP Coprocessor.

Regards

[Baldhead]

Hi,

A solution similar to this one looks interesting for a wrover board, especially for the esp32-s3 chip.

Flash memory and ram memory in a single package with one shared dtr octal spi bus interface.

OR

Flash memory and ram memory in a single package with two dtr sqi bus interface.

https://www.prnewswire.com/news-release ... 56587.html