Met guys in Shenzhen claiming making a 100% synchronous refresh free DRAM

[PaulNi]

http://www.xingmem.com/en/product_xm7a.php

Quite an interesting development, what do you think? Inside the chip, there are multiple banks one of which is refreshed during each clock cycle. When read comes when for the bank being refreshed, its content is restored using ECC during the same clock cycle, and same is true for write. All ECC logic is fabbed on the same die apparently.

Looks to me a way more potent thing than most PSRAM designs.

[WiFive]

Are they going to put a serial interface on it?

[PaulNi]

Are they going to put a serial interface on it?

All seem to be parallel. I think it will not make a big problem for them to put SPI/QSPI iface inside, if they will see big enough market there. I surely remember they were talking something about MCU market and some form of serial iface was at least contemplated for their 9A line http://www.xingmem.com/en/application.php