What would you like to see in The Next Chip?
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dzRBRglobal
- Posts: 11
- Joined: Thu Jul 26, 2018 3:20 pm
Re: What would you like to see in The Next Chip?
An official IDE based on eclipse from ESP would be great
Re: What would you like to see in The Next Chip?
Or official Visual Studio Code IDF/Debug/C/C++/C# plug-in would be more awesomedzRBRglobal wrote:An official IDE based on eclipse from ESP would be great
Re: What would you like to see in The Next Chip?
It sounds like all the important points have been covered, so this is merely another vote for the following:
The minimum:
- More pins (no need to go crazy, 6-10 or so is fine).
- No overlap of bootstrap pins with normal IO. Or the requirement for bootstrap pins eliminated (somehow).
- All the hardware bug fixes that will naturally come from being able to spin a new design with improved IP.
Very nice to have:
- USB DFU bootloading [in the ROM] (all other USB modes will naturally follow but the ability to have a bootstrap pin that initiates USB DFU mode would eliminate the need for a external USB-UART IC). Better still, if the bootstrap pin could trigger both a USB DFU and USB Serial profile to appear, that would solve the 'getting serial console at boot time' issue.
- Some sort of timer-triggered SPI transaction with DMA support.
The use case is an ADC like the ADS8688 where the sampling is triggered from the CS line going low, so you want your CS toggling rate to be precise and jitter-free.
- A 3rd 'user' SPI peripheral.
Things that I read in this thread that are interesting but not of immediate use to me:
- Support for more RF types (5GHz, LoRa, etc).
- Ethernet PoE management.
Things I think are better suited to implementing in external ICs by the end user or in a module:
- Higher bit/precision ADC/DAC. Just making the existing ADC linear would be an excellent improvement.
The minimum:
- More pins (no need to go crazy, 6-10 or so is fine).
- No overlap of bootstrap pins with normal IO. Or the requirement for bootstrap pins eliminated (somehow).
- All the hardware bug fixes that will naturally come from being able to spin a new design with improved IP.
Very nice to have:
- USB DFU bootloading [in the ROM] (all other USB modes will naturally follow but the ability to have a bootstrap pin that initiates USB DFU mode would eliminate the need for a external USB-UART IC). Better still, if the bootstrap pin could trigger both a USB DFU and USB Serial profile to appear, that would solve the 'getting serial console at boot time' issue.
- Some sort of timer-triggered SPI transaction with DMA support.
The use case is an ADC like the ADS8688 where the sampling is triggered from the CS line going low, so you want your CS toggling rate to be precise and jitter-free.
- A 3rd 'user' SPI peripheral.
Things that I read in this thread that are interesting but not of immediate use to me:
- Support for more RF types (5GHz, LoRa, etc).
- Ethernet PoE management.
Things I think are better suited to implementing in external ICs by the end user or in a module:
- Higher bit/precision ADC/DAC. Just making the existing ADC linear would be an excellent improvement.
Re: What would you like to see in The Next Chip?
OK. Here's something awesome for the longer term: put an FPGA on the chip!
FPGA's are going to be big in the maker community in the coming years.
Currently Microchip have the CLC which is of limited use. Cypress have the PSOC, but this is just used to replace the standard peripherals others include anyway. Xilinx have the expensive Zynq SOC.
All of these are are long way from the ESP32 though, so putting an FPGA on the ESP32 would be a world beater.
You wouldn't need much for a first generation chip, a few hundred LUTs would be a good starter. I doubt you would need to write much in the way of tools for it either. Just the data base backend for the Yosys/Nextpnr project and you have a verilog toolchain.
How about it?
FPGA's are going to be big in the maker community in the coming years.
Currently Microchip have the CLC which is of limited use. Cypress have the PSOC, but this is just used to replace the standard peripherals others include anyway. Xilinx have the expensive Zynq SOC.
All of these are are long way from the ESP32 though, so putting an FPGA on the ESP32 would be a world beater.
You wouldn't need much for a first generation chip, a few hundred LUTs would be a good starter. I doubt you would need to write much in the way of tools for it either. Just the data base backend for the Yosys/Nextpnr project and you have a verilog toolchain.
How about it?
Re: What would you like to see in The Next Chip?
That would be probably to much to expect and the cost would be high.
But including something like CCL (Configurable Custom Logic on Atmel/Microchip ATXMEGA) should be possible and usefull.
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tvoneicken
- Posts: 33
- Joined: Tue Nov 17, 2015 5:20 am
Re: What would you like to see in The Next Chip?
How about lower power consumption while maintaining an association with an AP?
The esp8266 has been a real disappointment in this respect. The esp32 doesn't seem much better. Some things are software and not hardware issues, such as being able to force light sleep for extended periods and just wake up frequently enough to renew the association and quickly ping some server (e.g. mqtt) to get an input. But maybe a hardware state machine, or better crypto support could reduce the power necessary for all this.
The esp8266 has been a real disappointment in this respect. The esp32 doesn't seem much better. Some things are software and not hardware issues, such as being able to force light sleep for extended periods and just wake up frequently enough to renew the association and quickly ping some server (e.g. mqtt) to get an input. But maybe a hardware state machine, or better crypto support could reduce the power necessary for all this.
Re: What would you like to see in The Next Chip?
How about
1) USB Type C Power Delivery support with on-chip 4.2V Lithium battery charging and power management
2) A good DSP
3) Dedicated FPU
4) CCM/TCM for cryptography
5) Bluetooth 5.0 with support for all audio format (including LDAC and HWA)
6) Multi-band WiFi (including AC, AD, AX and AY ... cause why not)
7) More memory (including L1, L2 and L3 cache, larger RAM and ROM) Support for addressing HUGE external RAM (how about DDR4)
8) Support for USB 3.2 (lets push it to the extreme)
1) USB Type C Power Delivery support with on-chip 4.2V Lithium battery charging and power management
2) A good DSP
3) Dedicated FPU
4) CCM/TCM for cryptography
5) Bluetooth 5.0 with support for all audio format (including LDAC and HWA)
6) Multi-band WiFi (including AC, AD, AX and AY ... cause why not)
7) More memory (including L1, L2 and L3 cache, larger RAM and ROM) Support for addressing HUGE external RAM (how about DDR4)
8) Support for USB 3.2 (lets push it to the extreme)
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dzRBRglobal
- Posts: 11
- Joined: Thu Jul 26, 2018 3:20 pm
Re: What would you like to see in The Next Chip?
I would not be surprised if there comes perhabs a cloud remotly IDE for online compile and debug...dzRBRglobal wrote: ↑Fri Dec 07, 2018 5:33 pmAny official IDE with robust and easy to use debug would be great
i did think this last time more times, could be possible
anyway
best wishes
rudi
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love it, change it or leave it.
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問候飛出去的朋友遍全球魯迪
love it, change it or leave it.
-------------------------------------
問候飛出去的朋友遍全球魯迪
Re: What would you like to see in The Next Chip?
Programmable sample time on the ADC.
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