Minimum requirements to start the Hardware Counter

[SpenZerX]

Hello,

will the hardware counter start immediately when it is correct configured? Or is any trigger/start required?

In my tests the count register is always 0x0000, (not counting). I cant get it to count.
Goal of my tests was to count level changes on one gpio-pin (22).
I am not using the IDF driver.
The counter 0 is not paused. And not cleared.

I played with the counter-settings and verified them by a memory dump. My app parses the settings to the hardware.
define myS0 esp32_S0 CNT_UNIT=0&CH0_POS_MODE=inc_counter&CH0_NEG_MODE=inc_counter&CH0_HCTRL_MODE=no_modification&CH0_LCTRL_MODE=no_modification&THR_L_LIM_EN=Disabled&THR_H_LIM_EN=Disabled&THR_ZERO_EN=Disabled&THR_THRES0_EN=Disabled&THR_THRES1_EN=Disabled&FILTER_EN=Disabled


I searched for the problem. What i did before setting up counter 0 itself:

// enable the counter
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PCNT_CLK_EN);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PCNT_RST);

// config the gpio + gpio_matrix_in
pcnt_unit_t unit = 0;
pcnt_channel_t channel = 0;
int pulse_io = 22;
int ctrl_io = 21;

int input_sig_index = (channel == 0 ? PCNT_SIG_CH0_IN0_IDX + 4 * unit : PCNT_SIG_CH1_IN0_IDX + 4 * unit);
int ctrl_sig_index = (channel == 0 ? PCNT_CTRL_CH0_IN0_IDX + 4 * unit : PCNT_CTRL_CH1_IN0_IDX + 4 * unit);
if(pulse_io >= 0) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[pulse_io], PIN_FUNC_GPIO);
gpio_set_direction(pulse_io, GPIO_MODE_INPUT);
gpio_set_pull_mode(pulse_io, GPIO_PULLUP_ONLY);
gpio_matrix_in(pulse_io, input_sig_index, 0);
}
if(ctrl_io >= 0) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[ctrl_io], PIN_FUNC_GPIO);
gpio_set_direction(ctrl_io, GPIO_MODE_INPUT);
gpio_set_pull_mode(ctrl_io, GPIO_PULLUP_ONLY);
gpio_matrix_in(ctrl_io, ctrl_sig_index, 0);
}

Is this the minimum setup to start playing with the Counter?

[SpenZerX]

Hi i have done some further test with the hardware counter and i think your documentation is not clear.

Your driver may also be affected. Have you tested that your code will clear a counter that is not zero?

esp_err_t pcnt_counter_clear(pcnt_unit_t pcnt_unit)
{
PCNT_CHECK(pcnt_unit < PCNT_UNIT_MAX, PCNT_UNIT_ERR_STR, ESP_ERR_INVALID_ARG);
PCNT_ENTER_CRITICAL(&pcnt_spinlock);
PCNT.ctrl.val &= (~(BIT(PCNT_PLUS_CNT_RST_U0_S + (pcnt_unit * 2))));
PCNT_EXIT_CRITICAL(&pcnt_spinlock);
return ESP_OK;
}


Register 8.9: PCNT_CTRL_REG (0x00b0)
PCNT_CNT_PAUSE_Un Set this bit to freeze unit n’s counter. (R/W)
PCNT_PLUS_CNT_RST_Un Set this bit to clear & stop unit n’s counter. Clear the bit to start counting (if not paused) (R/W) (This bit is initially set)

[SpenZerX]

This should clear the counter:

esp_err_t pcnt_counter_clear(pcnt_unit_t pcnt_unit)
{
PCNT_CHECK(pcnt_unit < PCNT_UNIT_MAX, PCNT_UNIT_ERR_STR, ESP_ERR_INVALID_ARG);
PCNT_ENTER_CRITICAL(&pcnt_spinlock);
PCNT.ctrl.val |= (BIT(PCNT_PLUS_CNT_RST_U0_S + (pcnt_unit * 2)));
// may be a delay here ...
PCNT.ctrl.val &= (~(BIT(PCNT_PLUS_CNT_RST_U0_S + (pcnt_unit * 2))));
PCNT_EXIT_CRITICAL(&pcnt_spinlock);
return ESP_OK;
}

[Superkurt]

I've also found that the current implementation of pcnt_counter_clear is not working. If I call the function the counter will not be reset to zero. But with the code SpenZerX suggested it's working.

Btw: I found that the initialization of the counter can't be done with pcnt_set_mode and pcnt_set_pin. I though that only these two calls can initialize the counter but that's not working because the call to periph_module_enable(PERIPH_PCNT_MODULE) should also be done.

Maybe someone from the espressif team could fix the pcnt_counter_clear api...

[joster]

THANK YOU SpenZerX for posting that code! I was tearing my hair out trying to get that PCNT peripheral to clear its counter.

Espressif, please get this fix integrated into the ESP-IDF.

[onpa_esp32]

Joster, Superkurt: Any solution with PCNT and pulse Counting of esp32.

Thanks,
Ondrej

[Lamonde]

This should clear the counter:

esp_err_t pcnt_counter_clear(pcnt_unit_t pcnt_unit)
{
PCNT_CHECK(pcnt_unit < PCNT_UNIT_MAX, PCNT_UNIT_ERR_STR, ESP_ERR_INVALID_ARG);
PCNT_ENTER_CRITICAL(&pcnt_spinlock);
PCNT.ctrl.val |= (BIT(PCNT_PLUS_CNT_RST_U0_S + (pcnt_unit * 2)));
// may be a delay here ...
PCNT.ctrl.val &= (~(BIT(PCNT_PLUS_CNT_RST_U0_S + (pcnt_unit * 2))));
PCNT_EXIT_CRITICAL(&pcnt_spinlock);
return ESP_OK;
}

Thank you!
That saved tons of time.
Cheers

[Don Warr]

SpenZerX First post was, "Minimum requirements to start the Hardware Counter" then went to resetting the counter,, But can someone please confirm that his code in the 1 post is the Minimum requirements.... to evaluate the pulse counter.. Any thoughts would be appreciated.. Thank's..