Level 5 interrupt debugging issues

[michprev]

Hi,
I have some issues while playing with GDB and level 5 interrupts.

My vecbase is at 0x40080000 (the same as ESP-IDF uses).
Level 5 interrupt vector code:

Code: Select all

    .org    0x240
    .section .vectors
    .align 4
    .global _Level5InterruptVector
_Level5InterruptVector:

    wsr.excsave5    a0

    rsr.interrupt   a0
    bbci            a0, 16, _Level5InterruptEnd

    rsr.intenable   a0
    bbci            a0, 16, _Level5InterruptEnd

    mov             a0, sp
    addi            sp, sp, -XT_STK_FRMSZ
    s32i            a0, sp, XT_STK_A1
    s32i            a2, sp, XT_STK_A2
    s32i            a3, sp, XT_STK_A3

    call0           _Timer2Interrupt

    l32i            a3, sp, XT_STK_A3
    l32i            a2, sp, XT_STK_A2
    l32i            sp, sp, XT_STK_A1

_Level5InterruptEnd:

    rsr.epc5        a0
    rsr.excsave5    a0

    rfi 5

I am enabling Timer2 interrupt like so:

Code: Select all

void System_Time_Init(uint32_t ticks)
{
    extern uint32_t _timer_ccompare;
    _timer_ccompare = ticks;

    extern uint32_t _timer_ticks;
    _timer_ticks = 0;

    uint32_t ccount;
    __asm__ __volatile__ ("rsr.ccount %0" : "=r"(ccount));

    ccount += ticks;
    __asm__ __volatile__ ("wsr.ccompare2 %0" :: "r"(ccount));


    uint32_t intenable;
    __asm__ __volatile__ ("rsr.intenable %0" : "=r"(intenable));

    intenable |= 1u << 16u;

    __asm__ __volatile__ ("wsr.intenable %0" :: "r"(intenable));
}

I am setting gdb breakpoint at _Level5InterruptVector.
After "rsr.interrupt a0" there is 0x8040 in $a0. That means that interrupts no. 6 and 15 are triggered. But neither of them is level 5 interrupt.
It might be this issue https://github.com/espressif/openocd-esp32/issues/47.

After "rsr.epc5 a0" $a0 contains 0x40080240 which is start of level 5 interrupt vector. That means that after CPU leaves interrupt vector it jumps back into it again.