Timer.2 interrupt does not set bit in INTERRUPT register

[michprev]

Hi,
I would like to use Timer.2 CPU interrupt. It is priority level 5 interrupt (not C servicable).
I am initializating it like this:

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void System_Time_Init()
{
    uint32_t ccount;
    __asm__ __volatile__ ("rsr.ccount %0" : "=r"(ccount));

    ccount += 10000;
    __asm__ __volatile__ ("wsr.ccompare2 %0" :: "r"(ccount));

    uint32_t intenable;
    __asm__ __volatile__ ("rsr.intenable %0" : "=r"(intenable));

    intenable |= 1u << 16u;

    __asm__ __volatile__ ("wsr.intenable %0" :: "r"(intenable));
}

CPU enters level 5 interrupt vector. There I check that bit 16 in INTENABLE and INTERRUPT registers is set. But when I do

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rsr.interrupt a0

a0 contains 0x0 (no interrupts triggered). Isn't it strange? The only interrupt that does not set bit in INTERRUPT register should be NMI.

[michprev]

Probably bug in OpenOCD/GDB. Will post it on https://github.com/espressif/openocd-esp32.