deep sleep wake up cause is not tue

selim_bayhan
Posts: 5
Joined: Sun Apr 15, 2018 7:48 am

deep sleep wake up cause is not tue

Postby selim_bayhan » Tue Apr 24, 2018 7:15 pm

The code at the end of this post working perfect. It gives the exact wake up reason when it wakes up from deep sleep. For power consumption efficiency I want to close the peripherals with a GPIO pin ( pin 4) connected to a MOSFET circuit . So I decided to add a

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mgos_gpio_write(4,0); 
statement before going to sleep . After wake up I add the following statements to the starting off the program.

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mgos_gpio_set_mode(4, MGOS_GPIO_MODE_OUTPUT);
mgos_gpio_write(4,1);
after adding these statements the wake up reason becomes undefined. What will be the possible cause of this behavior?

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#include "mgos.h"
#include "rom/rtc.h"
#include "driver/rtc_io.h"
#include "esp_sleep.h"
#include "mgos_gpio.h"

#define BUTTON_PIN_BITMASK 0x200000000 // 2^33 in hex - pin 33 is  used for wakeup

//  DEEP SLEEP HELPER FUNCTION: 
//  
static void gotosleep(){

  const int wakeup_time_sec = 60;
  printf("Enabling timer wakeup, %ds\n", wakeup_time_sec);
  esp_sleep_enable_timer_wakeup(wakeup_time_sec * 1000000);

  esp_err_t pdConfigError = esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
  if (pdConfigError != ESP_OK) {
    printf("pdConfigError");
  }

  esp_err_t enableWakeupError = esp_sleep_enable_ext1_wakeup(BUTTON_PIN_BITMASK, ESP_EXT1_WAKEUP_ANY_HIGH);
  if (enableWakeupError != ESP_OK) {
    printf("enableWakeupError");
  }

  printf("All done.  Going to sleep in ");
  for(int i=5; i>0; --i){
    printf("%d...\n", i);
    sleep(2);
  }
  printf("Good night.\n");

  //mgos_gpio_write(4,0);

  esp_deep_sleep_start();
}

//  HELPER FUNCTION: Decode the reason for resetting. 
//  Refer to:
//    https://github.com/espressif/arduino-esp32/blob/master/libraries/ESP32/examples/ResetReason/ResetReason.ino
//    https://github.com/espressif/esp-idf/blob/master/components/esp32/include/rom/rtc.h
//
void why_reset(){
  int reset_reason = rtc_get_reset_reason(0); 
  printf("Reset Reason (%d): ", reset_reason);

  switch (reset_reason) {
    case 1  : printf("Vbat power on reset");break;
    case 3  : printf("Software reset digital core");break;
    case 4  : printf("Legacy watch dog reset digital core");break;
    case 5  : printf("Deep Sleep reset digital core");break;
    case 6  : printf("Reset by SLC module, reset digital core");break;
    case 7  : printf("Timer Group0 Watch dog reset digital core");break;
    case 8  : printf("Timer Group1 Watch dog reset digital core");break;
    case 9  : printf("RTC Watch dog Reset digital core");break;
    case 10 : printf("Instrusion tested to reset CPU");break;
    case 11 : printf("Time Group reset CPU");break;
    case 12 : printf("Software reset CPU");break;
    case 13 : printf("RTC Watch dog Reset CPU");break;
    case 14 : printf("for APP CPU, reseted by PRO CPU");break;
    case 15 : printf("Reset when the vdd voltage is not stable");break;
    case 16 : printf("RTC Watch dog reset digital core and rtc module");break;
    default : printf("NO_MEAN");
  }  
  printf("\n");
}

//  HELPER FUNCTION: Decode our reason for waking.
//
void why_wake(){
  int wake_cause = esp_sleep_get_wakeup_cause();
  printf("Wake Cause (%d): ", wake_cause);
  switch (wake_cause) {
    case 1  : printf("Wakeup caused by external signal using RTC_IO");break;
    case 2  : printf("Wakeup caused by external signal using RTC_CNTL");break;
    case 3  : printf("Wakeup caused by timer");break;
    case 4  : printf("Wakeup caused by touchpad");break;
    case 5  : printf("Wakeup caused by ULP program");break;
    default : printf("Undefined.  In case of deep sleep, reset was not caused by exit from deep sleep.");
  } 
  printf("\n");
}

// Read the sensor via timer
//
static void sensor_timer_cb(void *arg){
  if(mgos_gpio_read(2)){
    printf("Door is Open!  Do stuff....\n");
  } else {
    printf("Door is closed, going to sleep.\n");
    gotosleep();
  }
}

enum mgos_app_init_result mgos_app_init(void) {
  printf("-------------- STARTING APPLICATION -------------\n");
  why_reset();
  why_wake();

  int sleep_pin = 2;
  rtc_gpio_deinit(sleep_pin);
  mgos_gpio_set_mode(sleep_pin, MGOS_GPIO_MODE_INPUT);
  mgos_gpio_set_pull(sleep_pin, MGOS_GPIO_PULL_UP);

  //mgos_gpio_set_mode(4, MGOS_GPIO_MODE_OUTPUT);
  //mgos_gpio_write(4,1);

  mgos_set_timer(2000, MGOS_TIMER_REPEAT, sensor_timer_cb, NULL);

  return MGOS_APP_INIT_SUCCESS;
}

ESP_igrr
Posts: 2071
Joined: Tue Dec 01, 2015 8:37 am

Re: deep sleep wake up cause is not tue

Postby ESP_igrr » Thu Apr 26, 2018 7:47 am

What does your why_reset function print in the case when why_wake prints incorrect cause?

Can you post the full UART output, including output from ROM bootloader, which starts with "ets Jun 8 2016" line?

selim_bayhan
Posts: 5
Joined: Sun Apr 15, 2018 7:48 am

Re: deep sleep wake up cause is not tue

Postby selim_bayhan » Fri Apr 27, 2018 8:05 pm

You can find the UART output below. I have a device connected to UART and it is powered with the mosfet circuiy connected to pin 4. When I disconnect this uart device that is connected to pin 16 and 17 I get the true wake up cause. Below output is generated when uart device is connected . It gives Software reset CPU wakeup.

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[Apr 27 22:58:23.929] ets Jun  8 2016 00:22:57
[Apr 27 22:58:23.929] 
[Apr 27 22:58:23.929] rst:0xc (SW_CPU_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
[Apr 27 22:58:23.929] configsip: 0, SPIWP:0xee
[Apr 27 22:58:23.929] clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
[Apr 27 22:58:23.929] mode:DIO, clock div:2
[Apr 27 22:58:23.929] load:0x3fff0018,len:4
[Apr 27 22:58:23.929] load:0x3fff001c,len:5336
[Apr 27 22:58:23.929] load:0x40078000,len:0
[Apr 27 22:58:23.929] ho 12 tail 0 room 4
[Apr 27 22:58:23.929] load:0x40078000,len:14536
[Apr 27 22:58:23.929] entry 0x4007903c
[Apr 27 22:58:23.976] [0;32mI (30) boot: ESP-IDF v3.0-rc1-r7 2nd stage bootloader[0m
[Apr 27 22:58:23.976] [0;32mI (30) boot: compile time 20:26:50[0m
[Apr 27 22:58:23.976] [0;32mI (30) boot: Enabling RNG early entropy source...[0m
[Apr 27 22:58:23.976] [0;32mI (35) boot: SPI Speed      : 40MHz[0m
[Apr 27 22:58:23.976] [0;32mI (40) boot: SPI Mode       : DIO[0m
[Apr 27 22:58:23.976] [0;32mI (44) boot: SPI Flash Size : 4MB[0m
[Apr 27 22:58:23.976] [0;32mI (48) boot: Partition Table:[0m
[Apr 27 22:58:23.976] [0;32mI (51) boot: ## Label            Usage          Type ST Offset   Length   Flags[0m
[Apr 27 22:58:23.976] [0;32mI (59) boot:  0 nvs              WiFi data        01 02 00009000 00004000 00000000[0m
[Apr 27 22:58:24.020] [0;32mI (67) boot:  1 otadata          OTA data         01 00 0000d000 00002000 00000000[0m
[Apr 27 22:58:24.020] [0;32mI (76) boot:  2 app_0            OTA app          00 10 00010000 00180000 00000000[0m
[Apr 27 22:58:24.020] [0;32mI (84) boot:  3 fs_0             SPIFFS           01 82 00190000 00040000 00000000[0m
[Apr 27 22:58:24.020] [0;32mI (92) boot:  4 app_1            OTA app          00 11 001d0000 00180000 00000000[0m
[Apr 27 22:58:24.020] [0;32mI (100) boot:  5 fs_1             SPIFFS           01 82 00350000 00040000 00000000[0m
[Apr 27 22:58:24.020] [0;32mI (109) boot: End of partition table[0m
[Apr 27 22:58:24.053] [0;32mI (113) boot: OTA data 0: seq 0x00000001, st 0x10, CRC 0x157a2b85, valid? 1[0m
[Apr 27 22:58:24.053] [0;32mI (121) boot: OTA data 1: seq 0x00000000, st 0x00, CRC 0x00000000, valid? 0[0m
[Apr 27 22:58:24.053] [0;32mI (128) boot: Disabling RNG early entropy source...[0m
[Apr 27 22:58:24.053] [0;32mI (134) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x204bc (132284) map[0m
[Apr 27 22:58:24.115] [0;32mI (189) esp_image: segment 1: paddr=0x000304e4 vaddr=0x3ffb0000 size=0x02858 ( 10328) load[0m
[Apr 27 22:58:24.115] [0;32mI (193) esp_image: segment 2: paddr=0x00032d44 vaddr=0x40080000 size=0x00400 (  1024) load[0m
[Apr 27 22:58:24.115] [0;32mI (196) esp_image: segment 3: paddr=0x0003314c vaddr=0x40080400 size=0x0cec4 ( 52932) load[0m
[Apr 27 22:58:24.134] [0;32mI (226) esp_image: segment 4: paddr=0x00040018 vaddr=0x400d0018 size=0x99e3c (630332) map[0m
[Apr 27 22:58:24.391] [0;32mI (447) esp_image: segment 5: paddr=0x000d9e5c vaddr=0x4008d2c4 size=0x01b4c (  6988) load[0m
[Apr 27 22:58:24.391] [0;32mI (450) esp_image: segment 6: paddr=0x000db9b0 vaddr=0x400c0000 size=0x00064 (   100) load[0m
[Apr 27 22:58:24.391] [0;32mI (463) cpu_start: Pro cpu up.[0m
[Apr 27 22:58:24.393] [0;32mI (463) cpu_start: Single core mode[0m
[Apr 27 22:58:24.393] [0;32mI (463) heap_init: Initializing. RAM available for dynamic allocation:[0m
[Apr 27 22:58:24.393] [0;32mI (469) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM[0m
[Apr 27 22:58:24.393] [0;32mI (475) heap_init: At 3FFB8DD8 len 00027228 (156 KiB): DRAM[0m
[Apr 27 22:58:24.415] [0;32mI (481) heap_init: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM[0m
[Apr 27 22:58:24.415] [0;32mI (487) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM[0m
[Apr 27 22:58:24.415] [0;32mI (494) heap_init: At 4008EE10 len 000111F0 (68 KiB): IRAM[0m
[Apr 27 22:58:24.415] [0;32mI (500) cpu_start: Pro cpu start user code[0m
[Apr 27 22:58:24.423] [0;32mI (182) cpu_start: Starting scheduler on PRO CPU.[0m
[Apr 27 22:58:24.455] mgos_init2           padylockv3 1.0 (20180426-192607/???)
[Apr 27 22:58:24.455] mgos_init2           Mongoose OS 2018042320 (20180423-202652/???)
[Apr 27 22:58:24.455] mgos_init2           CPU: 160 MHz, RAM: 295360 total, 255936 free
[Apr 27 22:58:24.455] mg_lwip_if_init      Mongoose 6.11, LwIP 1.5.0
[Apr 27 22:58:24.455] mg_ssl_if_init       mbed TLS 2.8.0
[Apr 27 22:58:24.455] mgos_hal_freertos_pr ESP-IDF v3.0-rc1-r7
[Apr 27 22:58:24.460] mgos_hal_freertos_pr Boot partition: app_0; flash: 4M
[Apr 27 22:58:24.468] mgos_vfs_dev_open    esp32part ({"label": "fs_0", "subtype": 130}) -> 0x3ffc1400
[Apr 27 22:58:24.477] mgos_vfs_mount       Mount SPIFFS @ / (dev 0x3ffc1400, opts {"encr": false}) -> 0x3ffc1410
[Apr 27 22:58:24.553] mgos_vfs_mount       /: size 233681, used: 22590, free: 211091
[Apr 27 22:58:24.615] mgos_sys_config_init MAC: 30AEA41AA634
[Apr 27 22:58:24.620] mgos_sys_config_init WDT: 30 seconds
[Apr 27 22:58:24.625] mg_rpc_channel_uart  0x3ffc1eec UART0
[Apr 27 22:58:24.629] mgos_wifi_setup      WiFi mode: AP
[Apr 27 22:58:24.633] esp32_wifi_set_mode  WiFi mode: AP
[Apr 27 22:58:24.638] E (608) wifi: esp_wifi_set_mode 782 wifi is not init
[Apr 27 22:58:24.643] I (618) wifi: wifi firmware version: c202b34
[Apr 27 22:58:24.646] I (618) wifi: config NVS flash: enabled
[Apr 27 22:58:24.650] I (618) wifi: config nano formating: disabled
[Apr 27 22:58:24.660] I (628) wifi: Init dynamic tx buffer num: 32
[Apr 27 22:58:24.665] I (638) wifi: Init data frame dynamic rx buffer num: 64
[Apr 27 22:58:24.670] I (638) wifi: Init management frame dynamic rx buffer num: 64
[Apr 27 22:58:24.676] I (648) wifi: wifi driver task: 3ffc3788, prio:23, stack:4096
[Apr 27 22:58:24.680] I (648) wifi: Init static rx buffer num: 10
[Apr 27 22:58:24.685] I (658) wifi: Init dynamic rx buffer num: 0
[Apr 27 22:58:24.691] I (658) wifi: wifi power manager task: 0x3ffc83c8 prio: 21 stack: 2560
[Apr 27 22:58:24.697] mgos_wifi_dev_ap_set WiFi AP: SSID Mongoose_1AA634, channel 6
[Apr 27 22:58:25.556] mgos_wifi_dev_ap_set WiFi AP IP: 192.168.4.1/255.255.255.0 gw 192.168.4.1, DHCP range 192.168.4.2 - 192.168.4.100
[Apr 27 22:58:25.625] [0;32mI (1588) phy: phy_version: 383.0, 79a622c, Jan 30 2018, 15:38:06, 0, 0[0m
[Apr 27 22:58:25.625] I (1588) wifi: mode : softAP (30:ae:a4:1a:a6:35)
[Apr 27 22:58:25.634] mgos_wifi_dev_ap_set WiFi AP: SSID Mongoose_1AA634, channel 6
[Apr 27 22:58:25.640] event_handler        event: 13
[Apr 27 22:58:25.646] -------------- STARTING APPLICATION -------------
[Apr 27 22:58:25.654] Wake Cause (0): Undefined.  In case of deep sleep, reset was not caused by exit from deep sleep.
[Apr 27 22:58:25.658] Reset Reason (12): Software reset CPU
[Apr 27 22:58:25.666] mgos_init            Init done, RAM: 294748 total, 221464 free, 221464 min free
[Apr 27 22:58:27.661] Door is Open!  Do stuff....

ESP_igrr
Posts: 2071
Joined: Tue Dec 01, 2015 8:37 am

Re: deep sleep wake up cause is not tue

Postby ESP_igrr » Sat Apr 28, 2018 6:34 am

That seems to match the bootloader output:

[Apr 27 22:58:23.929] rst:0xc (SW_CPU_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

So it looks like SW_CPU_RESET is indeed happening. Can you include a few of the previous lines of the log, perhaps there is some indication of what is going on?

selim_bayhan
Posts: 5
Joined: Sun Apr 15, 2018 7:48 am

Re: deep sleep wake up cause is not tue

Postby selim_bayhan » Sun Apr 29, 2018 8:50 pm

I understand the problem. But I do not know how I can solve it. When I look at the logs as you recommended. I found that there is a brownout detected and the cpu is restarted. Actually I got the the true wakeup cause but when the brownout detected a software reset occuring and I read this rest and wake up causes after restart. Here is the log that you want

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[Apr 29 23:39:31.681] -------------- STARTING APPLICATION -------------
[Apr 29 23:39:31.685] Reset Reason (5): Deep Sleep reset digital core
[Apr 29 23:39:31.691] Wake Cause (2): Wakeup caused by external signal using RTC_CNTL
[Apr 29 23:39:31.702] mgos_init            Init done, RAM: 295184 total, 222472 free, 222344 min free
[Apr 29 23:39:31.702] 
[Apr 29 23:39:31.702] Brownout detector was triggered
[Apr 29 23:39:31.702] 
[Apr 29 23:39:31.732] ets Jun  8 2016 00:22:57
I disabled brownout detection but nothing changed. I think I have to do something with hardware. Do you have any recommendations.?

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