NVS Read/Write Over Usage

[gregstewart90]

Is there a limit to the number of times I can write to or read from NVS? If I implement a timer with the ESP32 by updating the value total_time in NVS once a second by simply incrementing the value, will this cause problems? If there is a limitation, what are the best practices to avoid over use?

Code: Select all

void inc_total_time(){
	total_time++;
       nvs_handle my_handle;
	esp_err_t err = nvs_open(SYS_STORAGE_NAMESPACE, NVS_READWRITE, &my_handle);
	if (err != ESP_OK) {
		printf("Error (%d) opening NVS!\n", err);
	}
	err = nvs_set_i32(my_handle, "total_time", total_time);
	if (err != ESP_OK) {
		printf("ERROR (Close Storage): %d\n", err);
		return;
	}
	err = nvs_commit(my_handle);
	if (err != ESP_OK) {
		printf("ERROR(Commit Storage): %d\n", err);
		return;
	}
	nvs_close(my_handle);
}

[photomankc]

In general it's not a great idea to write to a single location constantly. EEPROM and FLASH both have limited write cycles before they can start to show errors reading back. I believe the NVS is implemented using some of the device's FLASH space.

Much depends on the implementation under the hood. If there is some wear-leveling going on it's not so bad as a single byte can be shuffled around to many actual write locations, greatly increasing the number of writes the FLASH can endure. If not, Just realize that you are writing to that single location 3,600 times per hour. Most flash is spec'd for between 10,000 and 100,000 write cycles. At the upper end that's ~28hrs before you exceed it writing to a single location.

With a small SRAM chip and a coin cell, you could write to it constantly for decades and not have to worry about wearing it out.

My approach was usually to avoid any continual periodic updates to EEPROM or FLASH. You are always chipping away at it using that method. Instead, I use a shutdown sequence to write what needs to be preserved prior to shutdown and read it back on startup. Alternatively, I have used I2C/SPI Real Time Clock chips just for their often included few tens or hundreds of bytes of RAM and ready coin cell backup ability when I need to store a few values constantly in case power is suddenly lost.


ETA: Another option is FRAM.... then you don't even need the coin cell.

[ESP_Sprite]

Yes, there is some wear, but the NVS wear levelling should attenuate that by a lot. Details are here, In your case, given that your key isn't too big, we can assume your entry in NVS is 64 bytes or so. Given that the default NVS partition size is 16K (for an OTA firmware), you can write such a key roughly 256 times before the NVS partition needs an erase cycle. Most flashchips I have seen are specced for 100000 write cycles, so you can store your timestamp 25600000 times. If you do that once a second, this means your flash will start wearing out in slightly less than a year. Now, you can attenuate this by making the nvs partition bigger: e.g. allocating 128K for this will result in a lifespan of 6 years.

[photomankc]

Nice to see wear-leveling is implemented. That will definitely greatly extend endurance.

I recall once where I was supposed to write 12 bytes once every 30 minutes to a static location on an EEPROM, but a bug in the timing code caused it to actually occur at the main loop cycle frequency of 20 times per second after I fiddled with it one more time. I only caught it after 15 minutes when I was looking at i2C for another reason. But that was 18,000+ writes to the EEPROM. I was not to happy about that. No wear leveling on those.

[lagrecjo]

Instead, I use a shutdown sequence to write what needs to be preserved prior to shutdown and read it back on startup.

Could you explain how to receive an event on power fail for this shutdown sequence implementation?