SPI configurable segmented transfer

Tanguy
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Joined: Thu Dec 09, 2021 9:33 pm

SPI configurable segmented transfer

Postby Tanguy » Tue Sep 24, 2024 7:17 am

We implemented an SPI driver that allows to write/read from/to circular buffers in continuous mode, managed by DMA.

With ESP32 : There is a register bit DMA_CONTINUE that can be set. With circular linked lists it is easy to get it running. Absolutely no cache miss or delays since all is managed by hardware.

With ESP32-C3 and other modules with GDMA : the register bit DMA_CONTINUE doesn't exist anymore. So we have to use configurable segmented transfer to achieve a continuous mode. The problem is there is a delay of 5 clock period that seems unavoidable between each segment. That leads to a loss of sampling frequency that we would like to avoid. Is there any other way ? Does the DMA_CONTINUE register bit still exists but not documented ?

ESP_Sprite
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Re: SPI configurable segmented transfer

Postby ESP_Sprite » Wed Sep 25, 2024 7:57 am

I think you only need DMA_CONTINUE if you mess with the DMA descriptor chain. If your circular buffer is exactly that (a static chain that happens to have the last descriptor pointing at the first), you should simply be able to let it run.

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ok-home
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Re: SPI configurable segmented transfer

Postby ok-home » Wed Sep 25, 2024 8:44 am

ESP_Sprite wrote:
Wed Sep 25, 2024 7:57 am
I think you only need DMA_CONTINUE if you mess with the DMA descriptor chain. If your circular buffer is exactly that (a static chain that happens to have the last descriptor pointing at the first), you should simply be able to let it run.


Unfortunately SPI with GDMA cannot receive/send in one transaction more than what is specified in SPI_MS_DATA_BITLEN
- 18 bit size, 262144 bits, even if we set the circular buffer on GDMA to continuously receive or transmit.

Tanguy
Posts: 10
Joined: Thu Dec 09, 2021 9:33 pm

Re: SPI configurable segmented transfer

Postby Tanguy » Wed Sep 25, 2024 8:03 pm

Exactly,

In ESP32 with DMA_CONTINUE set, the transactions are automatically chained with the same parameters (including same SPI_USR_MISO_DBITLEN) and no delay.

in ESP32-C3 the transactions can be chained using CST but with a mandatory reconf that cost a few clock cycles between each transactions.
Allowing to reconf between each transaction is a considerable improvement. Typically it is now possible to assert the CS line between transactions which was not possible with ESP32. However it is unfortunate that it is impossible to completely skip this reconf state when it is not needed.

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