ETM and ISR execution order

[gebov1]

Hello,

I was looking into this sample and noticed that I could not understand. https://github.com/espressif/esp-idf/tr ... re_hc_sr04.

The sample uses both an ISR of the hardware timer and the ETM matrix. In the ISR of the timer it is expected that the ETM channel has executed before the ISR is invoked, so the value from the register can be read. Is that always the case and is it documented somewhere ?

Thanks,
Martin

[ESP_Sprite]

With the current ESP-IDF, yes. ETM takes perhaps a handful (say 10 or 20 at max, probably less) of APB clock cycles (@80MHz) depending on clock domain crossings. Meanwhile, taking an interrupt means stashing the internal state of the CPU into memory, which easily takes something in the order of magnitude of a few hundred of cycles (@160 or 240MHz). In other words: unless you go through specific lengths to make the interrupt as fast as possible (e.g. with a high-level interrupt coded in assembly), the ETM event will always be faster than the interrupt.