Hello,
I would like to ask if it is possible to use Processor Instruction Extensions instructions like ee.vld.128.ip inside ISR handler ?
I was experimenting with RGB LCD demo and was trying to optimize memory copying in on_bounce handler to use series of ee.vld.128.ip / ee.vst.128.ip instructions in several q0, q1, q2 registers ... not really important.
The point is that when i execute ee.vld.128.ip in regular main_app code it works perfectly fine, but when i execute it on the same memory from ISR it crashes right away on that instruction. Is this expected or am i doing something wrong ?
My memory is placed in DRAM.
ESP32S3 - Processor Instruction Extensions + ISR
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Re: ESP32S3 - Processor Instruction Extensions + ISR
Probably not, not without a bunch of infrastructure.
Thing is that the PIE is implemented as a coprocessor, and in order to not have to save the context of coprocessors every time, FreeRTOS uses a trick: when it switches away from a task that used the coprocessor, it simply disables the coprocessor. If another task also uses it, it causes an exception which does the actual context saving and restoring. However, if only one task uses the coprocessor, the context can simply live in the coprocessor registers and never has to be swapped out.
This does mean that your interrupt is either A. overwriting the register context of a task when it's using the coprocessor, or B. causing an exception as the coprocessor is disabled.
Generally, we'd advise to keep your ISRs as light as possible, as is common on a RTOS. Use it to unblock a high-priority task, then do any actual work in the task itself.
Thing is that the PIE is implemented as a coprocessor, and in order to not have to save the context of coprocessors every time, FreeRTOS uses a trick: when it switches away from a task that used the coprocessor, it simply disables the coprocessor. If another task also uses it, it causes an exception which does the actual context saving and restoring. However, if only one task uses the coprocessor, the context can simply live in the coprocessor registers and never has to be swapped out.
This does mean that your interrupt is either A. overwriting the register context of a task when it's using the coprocessor, or B. causing an exception as the coprocessor is disabled.
Generally, we'd advise to keep your ISRs as light as possible, as is common on a RTOS. Use it to unblock a high-priority task, then do any actual work in the task itself.
Re: ESP32S3 - Processor Instruction Extensions + ISR
That explains a lot.
Yes i know i should keep ISRs lightweight but i was just going to experiment with PIE to learn the instruction set and i was surprised it crashes in ISR. There is no way to make GCC emit these instructions like ARM or x86 does with +simd/-msee so sadly the only way is through assembly :]
Yes i know i should keep ISRs lightweight but i was just going to experiment with PIE to learn the instruction set and i was surprised it crashes in ISR. There is no way to make GCC emit these instructions like ARM or x86 does with +simd/-msee so sadly the only way is through assembly :]
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