How to work with atomic esp32 operations (disabling interrupts)

Uint64_t
Posts: 7
Joined: Sat Feb 25, 2023 11:52 am

How to work with atomic esp32 operations (disabling interrupts)

Postby Uint64_t » Sat Feb 25, 2023 12:06 pm

I have a section of code where it is impossible for an interrupt to work. How can this be implemented? For example, the
instruction 1
instruction 2
disable interrupt
main instruction
enable interrupt
...

ESP_Sprite
Posts: 9730
Joined: Thu Nov 26, 2015 4:08 am

Re: How to work with atomic esp32 operations (disabling interrupts)

Postby ESP_Sprite » Sun Feb 26, 2023 5:30 am

You would use a critical section (docs).

Uint64_t
Posts: 7
Joined: Sat Feb 25, 2023 11:52 am

Re: How to work with atomic esp32 operations (disabling interrupts)

Postby Uint64_t » Sun Feb 26, 2023 10:39 am

Great! But if I need to block the interrupt only on the GPIO13 and do not touch the rest and it should be in the task

ESP_Sprite
Posts: 9730
Joined: Thu Nov 26, 2015 4:08 am

Re: How to work with atomic esp32 operations (disabling interrupts)

Postby ESP_Sprite » Mon Feb 27, 2023 12:06 am

?

vanBassum
Posts: 68
Joined: Sun Jan 17, 2021 11:59 am

Re: How to work with atomic esp32 operations (disabling interrupts)

Postby vanBassum » Mon Feb 27, 2023 9:12 am

instruction 1
instruction 2
gpio_set_intr_type(irqPin, GPIO_INTR_DISABLE);
main instruction
gpio_set_intr_type(irqPin, GPIO_INTR_HIGH_LEVEL);

Uint64_t
Posts: 7
Joined: Sat Feb 25, 2023 11:52 am

Re: How to work with atomic esp32 operations (disabling interrupts)

Postby Uint64_t » Mon Feb 27, 2023 6:06 pm

Thanks for the explanation!

ESP_Sprite
Posts: 9730
Joined: Thu Nov 26, 2015 4:08 am

Re: How to work with atomic esp32 operations (disabling interrupts)

Postby ESP_Sprite » Tue Feb 28, 2023 12:44 am

Note that on an ESP32, a critical section tends to be better for this, as disabling the IRQ has the race condition that the IRQ may already be in the process of being serviced on the other core. (Additionally, gpio_set_intr_type goes over a shared bus; I'm not sure if without a write fence that write is guaranteed to arrive before the next instruction.)

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