ESP32-P4 RISC-V dual core 400 MHz in the news

[burtrum]

Looks so good.

https://www.cnx-software.com/2023/01/06 ... ontroller/

With 3rd 40 MHz RISC-V LP Core
No wireless. With Ethernet.

Burtrum

[Hackswell]

Does anyone know if more details about the RISC-V cores have been released? Which extensions will each type have? I know that single-precision float is included in the main cores, but I'm curious as to the full set of extensions planned for each core type.

[Deouss]

Check this out

Sipeed M1s Dock BL808

Triple core MCU !
64MB ram
WiFi6
AI

[JimDrew]

Is there going to be some concrete information about the GPIO latency on these parts? I would hope that Espressif could figure out how to do single cycle GPIO by now. Taking hundreds of nanoseconds (with a sub-5ns clock) just to change a pin state is a huge limitation that none of their competitors have. You should be able to bypass the IO multiplexer and go straight to a pin with no latency with a 1:1 mapping, or with some small (defined) latency through the matrix if needed. This has been the biggest weakness for timing critical applications for these parts for many industries that Espressif could dominate in.

[ESP_Sprite]

You should be able to bypass the IO multiplexer and go straight to a pin with no latency with a 1:1 mapping, or with some small (defined) latency through the matrix if needed.

FWIW, the GPIO latency is a function of the bus they're on. If you need faster GPIO, we do support dedicated GPIO on most newer chips (S2 and up, iirc):
https://docs.espressif.com/projects/esp ... _gpio.html

[stuartiannaylor]

Hoping you get a dev kit out soon as wondering about ESP-Hosted and how you might implement a usb2serial bridge when there are 2x microcontrollers on a board?

Also if you do make a audio devkit could you just have a x4 channel ADC from the esp32-box and Dac but other than that a minimal dev-ket as that has so many uses.

[JimDrew]

FWIW, the GPIO latency is a function of the bus they're on. If you need faster GPIO, we do support dedicated GPIO on most newer chips (S2 and up, iirc):
https://docs.espressif.com/projects/esp ... _gpio.html

Thanks. I would also like to know if there is a defined interrupt latency for the P4 (and the S2/S3/C3). We have certain high-end applications that literally need to cycle count instructions (assembly code), but some things could be in C/C++ if the interrupt latency was consistent. I would be happy to move away from other micros if I could somehow make these parts work. We have had an allocation hold of our parts since June 2020 - apparently we need to order in the millions (instead of our measly hundred thousand) in order to get preferential treatment. We can't wait until June of this year (or so they say), so we are moving to something else in the coming months. Is there a release date for the P4? Engineering samples?

[mikemoy]

but some things could be in C/C++ if the interrupt latency was consistent.

Are you using Arduino or IDF?
If IDF have you tried going into menuconfig and try
"Run FreeRTOS only on first core"

[xien551]

Alternative to STM32F7/H7, good!

Hoping better performance of ADC, supporting PTP V2.

[landre]

Yeah so cool

I'm looking forward to getting my hands on it and trying out this MIPI DSI peripheral...
Any idea of the release date, and when it will be available?

Thanks,
Loïc