What would you like to see in The Next Chip?

[burtrum]

How about next 'module' ?

A built-in 32KHz crystal.
I don't want to design a board to experiment with RTC options.

Burtrum

[aristarchos]

An S3 with ETHERNET MAC.


No need for PHY, just the ETH MAC.
SPI connectivity solution to a eg SPI to ETH module has proved very poor, eg WT32-ETH01 (a plain ESP32 chip) outperforms the ESP32S3/W5500 hands down having 2 or 3 times the speed.
It is a bummer that the top of the line S3 has no ETH MAC.

[bernardthedog]

it would be nice to have easier multi thread features.

also a smaller board with less ports (with wifi). in most of my projects i don't need all the ports, and smaller size would be more important.

also some of the boards require me to hold the boot button to get into firmare mode, so please fix that.

Bluetooth 5.2 support

wifi 6 support

[bidrohini]

I want to see more analog pins.

[vanBassum]

I think I forgot this in my previous post, but I would really like some always unique hardware ID.

You can use the MAC-address for that, it's guaranteed to be unique.

Thanks, I wasn't sure.

[Franco]

A MIPI interface.

[mikemoy]

also some of the boards require me to hold the boot button to get into firmare mode, so please fix that.

Thats not an issue with the SOC, but the design programming hardware. There are so many knockoffs out there that do not impliment this correctly.

[ESP32_Arduino_user]

Thanks for the reply and the information about the ADC.
Unfortunately, it is very difficult to get along with the two cores in my application. All data is quickly recorded and passed on to various peripherals -> ESPnow + SD Card + UART + web server for GUI. Another core would significantly simplify development. The same application but with slower data acquisition runs stably. But at higher speeds, the WIFI communication hampers the timing of all peripherals.

- a 3-4 core version (I'm programming in Arduino IDE).
Why?
1. Core for all internal things e.g. WIFI, Bluetooth, Uart, SPI etc. -> system/event task
2. Core for fast / time-critical things like querying data from an ADC or similar -> only one task is running here, with my applications the task switching takes too long so that only one task can run
3. Core application, possibly several tasks (web server, save data on SD, UI etc.)
4th core optional from 3rd core

Wouldn't you be able to combine the 3rd and 1st core tasks and run this on a two-core CPU?

[svenbieg]

A C++ driver-layer.

[corz.org]

24 bit DAC.