ESP32-S3 GPIO20 remove startup glitch

yohnsee
Posts: 3
Joined: Sat Oct 14, 2023 8:21 pm

ESP32-S3 GPIO20 remove startup glitch

Postby yohnsee » Tue Oct 24, 2023 12:32 pm

Dear forum,
I designed a custom PCB board for the ESP32 S3 Wroom-1U module, and found an annoying behavior during testing. I configured the GPIO20 (USB D+) as a normal output pin in SETUP, but during chip boot cycle it gets pulled high for about 170ms. Do you know any method to disable this pull-up, as it is a serious problem for my circuit? As a last case scenario I can reroute the PCB and use other pin to control the output, but first I would like to get to the bottom of this.
So far I tried:
burnt DIS_USB_OTG efuse,
DIS_USB_JTAG
USB_PHY_SEL
DIS_USB_OTG_DOWNLOAD_MODE
None of the above helped.
Also tried to redefine #define USBPHY_DM_NUM 19 to an other pin in the first line in my .ino file, hoping it will reroute the GPIO matrix accordingly, but this didn't help either.

avrguru
Posts: 1
Joined: Thu May 16, 2024 5:41 am

Re: ESP32-S3 GPIO20 remove startup glitch

Postby avrguru » Thu May 16, 2024 5:48 am

The esp32-s3_datasheet doc mentions that there are Power-Up Glitches on many of the GPIO pins. See section 2.2, and Table 2-2, and especially footnote (2). No way to eliminate this effect via chip or module configuration, to my knowledge. Sorry there's not a better answer, this is something that probably needs a higher level of awareness by the community. Would be great to have this spelled out very prominently in the Technical Reference or Hardware Design manuals...

yohnsee
Posts: 3
Joined: Sat Oct 14, 2023 8:21 pm

Re: ESP32-S3 GPIO20 remove startup glitch

Postby yohnsee » Thu Aug 01, 2024 8:45 am

avrguru wrote:
Thu May 16, 2024 5:48 am
The esp32-s3_datasheet doc mentions that there are Power-Up Glitches on many of the GPIO pins. See section 2.2, and Table 2-2, and especially footnote (2). No way to eliminate this effect via chip or module configuration, to my knowledge. Sorry there's not a better answer, this is something that probably needs a higher level of awareness by the community. Would be great to have this spelled out very prominently in the Technical Reference or Hardware Design manuals...
Dear avrguru,
i wasn't around for a while, but thank you for the information. I was hoping, by tweaking the IO mux table or burning specific efuses would solve this problem, but I haven't found a solution for this. I modified my PCB in a way, that every output pin has a transistor, and these transistors do not have control voltage at startup, they get fed only 500-1000ms after boot. This way the output pins can be glitching, I do not care, my physical outputs do not get disturbed.

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