FreeRTOS, dual-core, two task, ...to slow

[ThomasK]

Thanks for the example with the timer ...
I made it work and was able to create a cycle with 1ms. Here you can see already minimal, it is made every 10ms a small break and stretched the signal minimal, but no problem, the whole cycle works well. But that is not an improvement to "normal task" with delay(1).
If I now change the value "#define OneK 1000" to 250, then I generate a cycle time of 0.25 ms, but again every 10ms a break, which now but already holds the signal for about 0.3 ms on the level.
If I now change the value "#define OneK 1000" to 100, then I create a cycle time of 0.1ms, but again every 10ms a break, which now but already holds the signal for about 0.2ms on the level.
The smaller I choose the value for OneK, the more "dirty" will the signal be. This is not a problem, but this dead time, which takes the "system", here every 10ms.
In my opinion, this version works clean only for a minimum of 0.5ms cycle.

[ESP_Sprite]

FWIW, you obviously can try to use the chips for anything you like if you so please, but you should know you're going a little bit against the architecture here... the Xtensa is quick because of lots of pipelining and a bunch of architectural details, but these same things make it slightly more expensive to handle interrupts than, say, and AVR. (FWIW, I think other CPUs of this class of speed/complexity may have similar issues.) That is the reason why it's not well-suited for timing-precise tasks like you're trying to do right now. As compensation, the chip comes with a gazillion of peripherals, general and specific, to do these things for you: as they're hardware, they're more suited to quick reaction times.

So by all means, feel free to experiment further, but do know you're somewhat in the realm of trying to hammer in a nail with a screwdriver here.