Interrupts and cores: can I free one core of any interrupts?

[markus_e]

I would like to know which of the two cores of the esp32 is used to run the background tasks like WIFI and Bluetooth.
Would it be possible, let's say core0 runs the background tasks, that I can use core1 and have it free of any interrupts?
I wrote a small test program which uses core1, just toggling one of the digital outputs, and observe that there is something which every 1 millisecond interrupts my program for about 7 microseconds.
Is there a separation of the management tasks (wifi, bt) to a certain core and can I somehow disable interrupts for the other core without side effects?

thanks for help!

[ESP_Sprite]

By default, everything runs on core 0. Core 1 should not have any interrupts out-of-the-box except for two: the FreeRTOS tick interrupt and the interrupt that is used to synchronize D-port accesses (workaround for a hw issue). You can disable the tick interrupt on CPU 1 if you also disable the idle task watchdog and don't need non-pre-emptive scheduling on that core. The D-port int isn't really disable-able, but it normally shouldn't trigger that often (unless you're using hardware-acccelerated crypto).

[Langelot]

Hello ESP_Sprite, What you said is interesting and exactly what I need, I have the same issue. How can you do that? I have tried vTaskSuspendAll() on core 1 but there is still a few miroseconds interruption each millisecond. I searched the internet but I can't find how to do disable the ticks and the idle task watchdog with arduino IDE.

Can you describe more precisely what you had in mind ? Some functions maybe?

Thank you.

[Richard42]

I ran into the exact same problem, and I was able to dig through the source code and figure it out. Here is how to disable and re-enable the timer tick interrupt on the current core:

Code: Select all

#include "freertos/xtensa_timer.h"
#include "esp_intr_alloc.h"

        ESP_INTR_DISABLE(XT_TIMER_INTNUM);
        // super time critical stuff
        ESP_INTR_ENABLE(XT_TIMER_INTNUM);