ESP32 Forum

Logic analyzer on ESP32 for self-diagnostics

- 16 channels.
- 40 megahertz. - maximum sample rate
- 32764 - maximum number of samples per frame (capture buffer). The volume is limited by the maximum size of free DRAM.
- 1 capture trigger channel. The trigger is organized on interrupts along the fronts. ESP32 interrupts are processed approximately 2 µs - Accordingly, the delay from the trigger to the beginning of the data, about 2 µs. In the latest version, the trigger has been moved to Hilevel interrupts ( level 5 ), the delay from the trigger to the beginning of the data has been reduced to 0.3 μS.
Uses the internal clock of samples, no need to set jumpers to supply sync pulses or use an external generator. Pins for sync pulses are not used.
- The analyzer allows you to work on the measured device. We install the software on the patient, configure the GPIO for channels (checked - GPIO, I2C, LED PWM, IRQ_GPIO, I think that the rest will also work), shows both input and output signals of the patient. Trigger restrictions in this mode - you cannot assign a trigger to a pin (GPIO) that has an interrupt assigned to the patient software (the analyzer will reconfigure itself) - in the latest version (interrupt level 5) the restriction is partially removed, but the trigger will fire on those fronts (levels ) that are assigned to the patient software.
- You can make the analyzer as a separate device, but I don't see much point. There are a sufficient number of cheap analogs with similar characteristics on the market. The main advantage of self-diagnostics is that we linked the software to the project and see what happens there. It is clear that the patient's software can already use the entire DRAM - then the volume of samples will greatly decrease - but we will still see at least the levels and a small number of samples.

https://github.com/ok-home/logic_analyzer

Hi

Logic analyzer now supports esp32s3
The maximum sample rate has been increased to 80 MHz for 8 channels.
Added PSRAM support

https://github.com/ok-home/logic_analyzer

Logic analyzer now supports esp32c3
esp32c3 -> use GPSPI2
60 kSamples -> 4 channels

https://github.com/ok-home/logic_analyzer

Added CLI interface for stable operation with PulseView when RAM is limited
- minimal RAM consumption
- a simple script logic_analyzer_cli/logic_analyzer_cli.py to save samples to a RowBin file (you need to add the PySerial dependency)
- script parameters are set in the la_cfg.json file (the file template is created automatically the first time the script is launched), GPIO,TRIGGER,TRBGGER EDGE,SAMPLES,SAMPLE RATE,NUMBER CHANNELS,RAM/PSRAM.
Connection to the program code
- logic_analyzer_cli/include/logic_analyzer_cli.h
- set ANALYZER_USE_CLI and UART parameters in menuconfig
- compile and download program code with connected logic_analyzer
- connect to UART
- run logic_analyzer_cli.py with the parameters set in the file la_cfg.json
connection to PulseView
- Import Raw binary logic data - a file created by the script
- setting the number of channels and sample frequency during the first import (esp32c3 - set 8 channels, 4 lower ones are used), in the
future, if these parameters do not change, just do Reload
- for UART0 the same restrictions as for the SUMP interface
advantages over SUMP interface
- look at the known PulseView bugs above - they are not here (except for UART0)
- simple GPIO configuration for channels via la_cfg.json

https://github.com/ok-home/logic_analyzer

Hi, I would like to use your logic analyzer for capturing CMD pin traffic of sdmmc interface. Is it possible to use CLK pin of sdmmc as clock source? sdmmc runs at 40 MHz in my case.

blade77 wrote: ↑

Mon Sep 09, 2024 8:26 pm

Hi, I would like to use your logic analyzer for capturing CMD pin traffic of sdmmc interface. Is it possible to use CLK pin of sdmmc as clock source? sdmmc runs at 40 MHz in my case.

The maximum sample frequency for esp32s3 is 80 mHz, you can see that there are signals, but this frequency is not enough for accurate measurements.
As an example esp32s3 spiflash dio mode 40 mHz

It sounds good. And can I use the CLK pin of the external sdmmc host as clock source instead of the internal clock?

blade77 wrote: ↑

Tue Sep 10, 2024 10:37 pm

It sounds good. And can I use the CLK pin of the external sdmmc host as clock source instead of the internal clock?

for ESP32S3 analyzer reads any data from any GPIO with sample rate which is set by internal oscillator of CAM module or ledc which is output on GPIO PCLK ( menuconfig ).
If you want to feed external PCLK as sample rate - please set in sample rate = 80 mHz, disconnect internal oscillators from GPIO PCLK, connect external PCLK to GPIO PCLK.
To disconnect internal oscillators from GPIO PCLK, you need to change these lines
https://github.com/ok-home/logic_analy ... ll.c#L137 or even simpler, without wiring, to your sdmmc host clock output
https://github.com/ok-home/logic_analy ... ll.c#L150
change to Note that real frequencies and delays may change ( external sdmmc host clock ) - not constant, it is intermittent.
And this does not guarantee proper capture, internally the СAM module is still clocked at 80 mHz.

Thank you so much. I am using ESP32 (pico) in my project. Will the same work with that as well?

blade77 wrote: ↑

Wed Sep 11, 2024 11:21 am

Thank you so much. I am using ESP32 (pico) in my project. Will the same work with that as well?

Sorry, on ESP32 (pico) the maximum sample rate is 40 mHz, and it is not so easy (and does not make sense) to connect an external PCLK.
The analyzer on ESP32 (pico) can reads any data from any GPIO, with a maximum sample rate of 40 mHz.
You may or may not see some signals at 40 MHz, but measuring a 40 mHz clock signal sampled at 40 mHz is not the best solution.