Logic analyzer on ESP32 for self-diagnostics

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ok-home
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Logic analyzer on ESP32 for self-diagnostics

Postby ok-home » Mon May 29, 2023 1:07 pm

Logic analyzer on ESP32 for self-diagnostics
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- 16 channels.
- 40 megahertz. - maximum sample rate
- 32764 - maximum number of samples per frame (capture buffer). The volume is limited by the maximum size of free DRAM.
- 1 capture trigger channel. The trigger is organized on interrupts along the fronts. ESP32 interrupts are processed approximately 2 µs - Accordingly, the delay from the trigger to the beginning of the data, about 2 µs. In the latest version, the trigger has been moved to Hilevel interrupts ( level 5 ), the delay from the trigger to the beginning of the data has been reduced to 0.3 μS.
Uses the internal clock of samples, no need to set jumpers to supply sync pulses or use an external generator. Pins for sync pulses are not used.
- The analyzer allows you to work on the measured device. We install the software on the patient, configure the GPIO for channels (checked - GPIO, I2C, LED PWM, IRQ_GPIO, I think that the rest will also work), shows both input and output signals of the patient. Trigger restrictions in this mode - you cannot assign a trigger to a pin (GPIO) that has an interrupt assigned to the patient software (the analyzer will reconfigure itself) - in the latest version (interrupt level 5) the restriction is partially removed, but the trigger will fire on those fronts (levels ) that are assigned to the patient software.
- You can make the analyzer as a separate device, but I don't see much point. There are a sufficient number of cheap analogs with similar characteristics on the market. The main advantage of self-diagnostics is that we linked the software to the project and see what happens there. It is clear that the patient's software can already use the entire DRAM - then the volume of samples will greatly decrease - but we will still see at least the levels and a small number of samples.

https://github.com/ok-home/logic_analyzer

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ok-home
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Re: Logic analyzer on ESP32 for self-diagnostics

Postby ok-home » Fri Aug 11, 2023 6:45 am

Hi

Logic analyzer now supports esp32s3
The maximum sample rate has been increased to 80 MHz for 8 channels.
Added PSRAM support

https://github.com/ok-home/logic_analyzer

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ok-home
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Re: Logic analyzer on ESP32 for self-diagnostics

Postby ok-home » Sat Aug 26, 2023 7:43 am

Logic analyzer now supports esp32c3
esp32c3 -> use GPSPI2
60 kSamples -> 4 channels

https://github.com/ok-home/logic_analyzer

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ok-home
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Re: Logic analyzer on ESP32 for self-diagnostics

Postby ok-home » Thu May 02, 2024 11:30 am

Added CLI interface for stable operation with PulseView when RAM is limited
- minimal RAM consumption
- a simple script logic_analyzer_cli/logic_analyzer_cli.py to save samples to a RowBin file (you need to add the PySerial dependency)
- script parameters are set in the la_cfg.json file (the file template is created automatically the first time the script is launched), GPIO,TRIGGER,TRBGGER EDGE,SAMPLES,SAMPLE RATE,NUMBER CHANNELS,RAM/PSRAM.
Connection to the program code
- logic_analyzer_cli/include/logic_analyzer_cli.h
- set ANALYZER_USE_CLI and UART parameters in menuconfig
- compile and download program code with connected logic_analyzer
- connect to UART
- run logic_analyzer_cli.py with the parameters set in the file la_cfg.json
connection to PulseView
- Import Raw binary logic data - a file created by the script
- setting the number of channels and sample frequency during the first import (esp32c3 - set 8 channels, 4 lower ones are used), in the
future, if these parameters do not change, just do Reload
- for UART0 the same restrictions as for the SUMP interface
advantages over SUMP interface
- look at the known PulseView bugs above - they are not here (except for UART0)
- simple GPIO configuration for channels via la_cfg.json

https://github.com/ok-home/logic_analyzer
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