ESP32 Forum

Hi all,

It seems that S3 has a hardware bug related to DMA segmented transaction protocol.

First, I used S2 as an SPI slave for my project. I used an SPI Slave HD example (\examples\peripherals\spi_slave_hd\segment_mode) for development. The S2 prepared a DMA transaction and I read it from the host in the following manner:
1. ~CS low
2. CMD4
3. Read data bytes
4. ~CS high
5. ~CS low
6. CMD8
7. ~CS high
This worked as charm. Then I migrated to S3.

I could not end DMA transfer. S3 seemed to ignore CMD8 completely.
First, I checked if SPI HD driver is OK, it is. Then I checked if interrupt mask register (SPI_DMA_INT_ENA_REG) is set, it is. The only way I could make things work was sending software interrupt for CMD8 by setting bit SPI_SLV_CMD8_INT_SET in SPI_DMA_INT_SET_REG register. And the interrupt then triggers, driver works, callback invokes, DMA transaction ends.

I didn't find anything in Errata for this stuff. My chip is rev0.1, had no chance to test rev0.2 so far.

My question to ESP32 hardware team: is that a real hardware bug?

Thanks.

Hi TS-Labs,

I have ESP32-S3 v0.1 also, and I can't get SPI slave HD segmented example to work at all. Did you manage to get it to work without modifying it? I have ESP32 as master and ESP32-S3 as slave, tested it with changing SPI to different pins and made also some little changes but all I can see with my logic analyzer that master pulses CS low/high and between that SCLK is working, nothing on the MOSI/MISO lines.

If I upload SPI slave example code from /examples/peripherals/spi_slave/ with same setup, all is fine and working, but normal slave drivers have no option to QUAD SPI that I need...

Thanks!

EDIT: Ok, found out the problem. There seems not to be code in ESP-IDF hal drivers for ESP32 that I use as master, so need to add them first (did some quick mods prior to test it is the problem) to check that I even can get it working right. I don't know why it is not supported, is there some hw differencies that prevents it from working right...