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Any difference between core 0 and core 1 in relation with SPI?

http://esp32.io/viewtopic.php?f=13&t=9414

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Any difference between core 0 and core 1 in relation with SPI?

Posted: Tue Feb 26, 2019 8:10 am
by SJKim0122
Hi, I'm working on AWS IoT solution which uses SPI for NFC read.

There's no issue when I'm using a task with core 0 like below:
xTaskCreatePinnedToCore(&tag_read_task, "tag_read_task", 8192, NULL, 0, NULL, 0);
However, if I use core 1 to read nfc tags with SPI communication,
xTaskCreatePinnedToCore(&tag_read_task, "tag_read_task", 8192, NULL, 0, NULL, 1);
It cannot read the tag info and sometimes even produces error like below.
Guru Meditation Error: Core 0 panic'ed (LoadProhibited). Exception was unhandled.
Core 0 register dump:
PC : 0x401381fc PS : 0x00060930 A0 : 0x8013845e A1 : 0x3ffdac00
0x401381fc: spi_device_queue_trans at /Users/ksj-pc/esp/esp-idf/components/driver/spi_master.c:762

A2 : 0x3ffd5990 A3 : 0x3ffdac70 A4 : 0xffffffff A5 : 0x00000000
A6 : 0x00000000 A7 : 0x00060023 A8 : 0x80090a01 A9 : 0x00000000
A10 : 0x00000020 A11 : 0x00000000 A12 : 0x00060920 A13 : 0x00000001
A14 : 0x0000cdcd A15 : 0x00060023 SAR : 0x0000001a EXCCAUSE: 0x0000001c
EXCVADDR: 0x00000038 LBEG : 0x4000c46c LEND : 0x4000c477 LCOUNT : 0x00000000

Backtrace: 0x401381fc:0x3ffdac00 0x4013845b:0x3ffdac40 0x400d7189:0x3ffdac70 0x400d7e96:0x3ffdacc0 0x400d592f:0x3ffdace0
0x401381fc: spi_device_queue_trans at /Users/ksj-pc/esp/esp-idf/components/driver/spi_master.c:762

0x4013845b: spi_device_transmit at /Users/ksj-pc/esp/esp-idf/components/driver/spi_master.c:885

0x400d7189: spiTxRx at /Users/ksj-pc/Documents/workspace_embedded/pium_fw/main/main.c:2163

0x400d7e96: as3911ReadMultipleRegisters at /Users/ksj-pc/Documents/workspace_embedded/pium_fw/main/as3911_com.c:127

0x400d592f: as3911task at /Users/ksj-pc/Documents/workspace_embedded/pium_fw/main/main.c:1165 (discriminator 1)

Rebooting...

So, is there any difference of Core 0 and 1 in this case? I can't even catch any hint.

Thank you for your help in advance.

Re: Any difference between core 0 and core 1 in relation with SPI?

Posted: Tue Feb 26, 2019 7:05 pm
by Ritesh
SJKim0122 wrote: ↑
Tue Feb 26, 2019 8:10 am
 Hi, I'm working on AWS IoT solution which uses SPI for NFC read.

There's no issue when I'm using a task with core 0 like below:
xTaskCreatePinnedToCore(&tag_read_task, "tag_read_task", 8192, NULL, 0, NULL, 0);
However, if I use core 1 to read nfc tags with SPI communication,
xTaskCreatePinnedToCore(&tag_read_task, "tag_read_task", 8192, NULL, 0, NULL, 1);
It cannot read the tag info and sometimes even produces error like below.
Guru Meditation Error: Core 0 panic'ed (LoadProhibited). Exception was unhandled.
Core 0 register dump:
PC : 0x401381fc PS : 0x00060930 A0 : 0x8013845e A1 : 0x3ffdac00
0x401381fc: spi_device_queue_trans at /Users/ksj-pc/esp/esp-idf/components/driver/spi_master.c:762

A2 : 0x3ffd5990 A3 : 0x3ffdac70 A4 : 0xffffffff A5 : 0x00000000
A6 : 0x00000000 A7 : 0x00060023 A8 : 0x80090a01 A9 : 0x00000000
A10 : 0x00000020 A11 : 0x00000000 A12 : 0x00060920 A13 : 0x00000001
A14 : 0x0000cdcd A15 : 0x00060023 SAR : 0x0000001a EXCCAUSE: 0x0000001c
EXCVADDR: 0x00000038 LBEG : 0x4000c46c LEND : 0x4000c477 LCOUNT : 0x00000000

Backtrace: 0x401381fc:0x3ffdac00 0x4013845b:0x3ffdac40 0x400d7189:0x3ffdac70 0x400d7e96:0x3ffdacc0 0x400d592f:0x3ffdace0
0x401381fc: spi_device_queue_trans at /Users/ksj-pc/esp/esp-idf/components/driver/spi_master.c:762

0x4013845b: spi_device_transmit at /Users/ksj-pc/esp/esp-idf/components/driver/spi_master.c:885

0x400d7189: spiTxRx at /Users/ksj-pc/Documents/workspace_embedded/pium_fw/main/main.c:2163

0x400d7e96: as3911ReadMultipleRegisters at /Users/ksj-pc/Documents/workspace_embedded/pium_fw/main/as3911_com.c:127

0x400d592f: as3911task at /Users/ksj-pc/Documents/workspace_embedded/pium_fw/main/main.c:1165 (discriminator 1)

Rebooting...

So, is there any difference of Core 0 and 1 in this case? I can't even catch any hint.

Thank you for your help in advance.
Hi,

I don't think that there is any relation between core 0 and 1 with SPI Interface.

Would you please let me know which SPI you are trying to access means normal SPI or HSPI?

Re: Any difference between core 0 and core 1 in relation with SPI?

Posted: Wed Feb 27, 2019 2:34 am
by SJKim0122
HSPI cause' I cannot use normal SPI to use for NFC modules according to this document: https://docs.espressif.com/projects/esp ... aster.html

Although I don't exactly understand what makes this issue, but the definite thing is that there's some difference between using core 0 and core 1.

Is there any document explaining the different role or some difference between those two?

Best Regards,
SJKim

Re: Any difference between core 0 and core 1 in relation with SPI?

Posted: Wed Feb 27, 2019 3:57 am
by Ritesh
SJKim0122 wrote: ↑
Wed Feb 27, 2019 2:34 am
 HSPI cause' I cannot use normal SPI to use for NFC modules according to this document: https://docs.espressif.com/projects/esp ... aster.html

Although I don't exactly understand what makes this issue, but the definite thing is that there's some difference between using core 0 and core 1.

Is there any document explaining the different role or some difference between those two?

Best Regards,
SJKim
Hi,

I think if you will see read the docs for ESP32 IDF in that you will get more useful details regarding CPU cores for that. Still let me know if you will not find anything regarding that.

Re: Any difference between core 0 and core 1 in relation with SPI?

Posted: Wed Feb 27, 2019 4:06 am
by ESP_Sprite
There should be zero difference, but by moving the task to core 1, you change the timing and interaction between tasks which can uncover otherwise hidden bugs.

- What ESP-IDF version are you using?
- Do you do all of your SPI initialization, access, etc in one single task, or is it divided over multiple tasks?
- Can you post your code here?

Re: Any difference between core 0 and core 1 in relation with SPI?

Posted: Thu Feb 28, 2019 2:23 am
by SJKim0122
What ESP-IDF version are you using?
- https://github.com/espressif/esp-idf/co ... ff1e5a48fc
(Commit no. 568da37)
- If I change the ESP-IDF version, it makes another error.
- I don't use any of SARADC1, SARADC2, HALL sensor, AMP, but use pin 36. So it might have some relation to WIFI pin 36 interrupt according to this document (Item no. 3.11): https://www.espressif.com/sites/default ... p32_en.pdf
- It was resolved by enabling interrupt after wifi_start on commit 568da37, but the problem restored on current master commit. I mean, it was resolved last time but came as an issue again after IDF update. For now, I can't change the pin number of my hardware. So let me know if there's any method to power off those sensors. I couldn't turn them off by calling adc_power_off()

Do you do all of your SPI initialization, access, etc in one single task, or is it divided over multiple tasks?
- Initialization in app_main() function, access in another task.
- If I add the same code in app_main(), it works as in Core 0, but still fails in Core 1.

Can you post your code here?
- This is not my own code so it would be difficult. It's part of my company source code.

I don't still exactly get it why this happens. I'm gonna try with some more ESP-IDF versions and let you know if there's any difference.
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