ESP32 Forum

Studying the SPI master driver, I find that we must configure a data structure called "spi_bus_config_t". Reading the documentation on it found here:

http://esp-idf.readthedocs.io/en/latest ... s_config_t

I find 5 pins need be configured:

• spid_io_num
• spiq_io_num
• spiclk_io_num
• spiwp_io_num
• spihd_io_num

Here comes the list of questions related to these names:

1) What does "spi_d" mean? I understand the SPI concept of "MOSI" ... but the concept of "d" means nothing to me.
2) What does "spi_q" mean? I understand the SPI concept of "MISO" ... but the concept of "q" means nothing to me.
3) What does "spi_wp" mean? I can't relate that to anything I am familiar with in the concept of SPI.
4) What does "spi_hd" mean? I can't relate that to anything I am familiar with in the concept of SPI.

The SPI flash peripheral actually was initially created to interface with SPI flash chips, which have a d, q, clk, wp and hd pin. I can imagine the SPI port pins are somewhat weird if you aren't familiar with that.

For MISO and MOSI, it is explained in the page you quoted:

int spid_io_num

GPIO pin for spi_d (=MOSI)signal, or -1 if not used.

int spiq_io_num

GPIO pin for spi_q (=MISO) signal, or -1 if not used.

spi_hd is the hold pin pf the flash chip, while spi_wp is for write protect. These pins aren't really used in the 1-bit SPI mode you'd normally use, but the 4-bit mode uses them as data lines.

I agree that the documentation can be slightly better wrt explaining this.

For the history ... as of the date of this post, the pins in SPI have been renamed to be:

int mosi_io_num – GPIO for MOSI or -1 if not used.
int miso_io_num – GPIO for MISO or -1 if not used.
int sclk_io_num – GPIO pin for CLK or -1 if not used.
int quadwp_io_num – Specify -1 if not used.
int quadhd_io_num – Specify -1 if not used.