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How to enable 32.768 kHz XTAL?

http://esp32.io/viewtopic.php?f=13&t=8083

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How to enable 32.768 kHz XTAL?

Posted: Sun Nov 18, 2018 6:43 pm
by esp_zag0
Hi,

I have connected 32.768 kHz crystal to pins 32 and 33 and to GND. I've selected "External 32kHz crystal" in menuconfig and left "Number of cycles for RTC_SLOW_CLK calibration" and "Bootstrap cycles for external 32kHz crystal" with default values (1024 and 5).

After compiling and flashing I get the following printout on power on:

Code: [Select all] [Expand/Collapse]
  1. I (30) boot: ESP-IDF v3.2-dev-39-gaaf12390e 2nd stage bootloader
  2. I (31) boot: compile time 19:13:39
  3. I (31) boot: Enabling RNG early entropy source...
  4. I (36) boot: SPI Speed      : 40MHz
  5. I (40) boot: SPI Mode       : DIO
  6. I (44) boot: SPI Flash Size : 4MB
  7. I (48) boot: Partition Table:
  8. I (52) boot: ## Label            Usage          Type ST Offset   Length
  9. I (59) boot:  0 nvs              WiFi data        01 02 00009000 00006000
  10. I (67) boot:  1 phy_init         RF data          01 01 0000f000 00001000
  11. I (74) boot:  2 factory          factory app      00 00 00010000 00100000
  12. I (82) boot: End of partition table
  13. I (86) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x06818 ( 26648) map
  14. I (104) esp_image: segment 1: paddr=0x00016840 vaddr=0x3ffb0000 size=0x0229c (  8860) load
  15. I (108) esp_image: segment 2: paddr=0x00018ae4 vaddr=0x3ffb229c size=0x00000 (     0) load
  16. I (112) esp_image: segment 3: paddr=0x00018aec vaddr=0x40080000 size=0x00400 (  1024) load
  17. 0x40080000: _iram_start at C:/msys32/home/user/esp-idf/components/freertos/xtensa_vectors.S:1685
  18.  
  19. I (122) esp_image: segment 4: paddr=0x00018ef4 vaddr=0x40080400 size=0x0711c ( 28956) load
  20. I (142) esp_image: segment 5: paddr=0x00020018 vaddr=0x400d0018 size=0x11e44 ( 73284) map
  21. 0x400d0018: _flash_cache_start at ??:?
  22.  
  23. I (168) esp_image: segment 6: paddr=0x00031e64 vaddr=0x4008751c size=0x015a0 (  5536) load
  24. 0x4008751c: rtc_clk_fast_freq_set at C:/msys32/home/user/esp-idf/components/soc/esp32/rtc_clk.c:445
  25.  
  26. I (171) esp_image: segment 7: paddr=0x0003340c vaddr=0x400c0000 size=0x00000 (     0) load
  27. I (175) esp_image: segment 8: paddr=0x00033414 vaddr=0x50000000 size=0x00000 (     0) load
  28. I (189) boot: Loaded app from partition at offset 0x10000
  29. I (190) boot: Disabling RNG early entropy source...
  30. I (196) cpu_start: Pro cpu up.
  31. I (199) cpu_start: Starting app cpu, entry point is 0x40080e58
  32. 0x40080e58: call_start_cpu1 at C:/msys32/home/user/esp-idf/components/esp32/cpu_start.c:225
  33.  
  34. I (0) cpu_start: App cpu up.
  35. I (210) heap_init: Initializing. RAM available for dynamic allocation:
  36. I (217) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
  37. I (223) heap_init: At 3FFB32F0 len 0002CD10 (179 KiB): DRAM
  38. I (229) heap_init: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
  39. I (235) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
  40. I (242) heap_init: At 40088ABC len 00017544 (93 KiB): IRAM
  41. I (248) cpu_start: Pro cpu start user code
  42. E (339) clk: RTC: Not found External 32 kHz XTAL. Switching to Internal 150 kHz RC chain
  43. I (14) cpu_start: Starting scheduler on PRO CPU.
  44. I (0) cpu_start: Starting scheduler on APP CPU.
GeSHi © Codebox Plus Extension

Is there something else I have to enable or configure to be activate XTAL?

PS. I'm using bare ESP-WROOM-32 with nothing but XTAL connected to it.

Thanks!

Re: How to enable 32.768 kHz XTAL?

Posted: Mon Nov 19, 2018 2:50 am
by ESP_Sprite
You also need to add a pair of load capacitors. See eg the ESP320-Wrover-Kit schematic for an example.
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