Best design principles for using SPI SRAM

[CharlesSeartech]

Hello,

I had to implement a large buffer to control write delays to the SD card and found it's not that simple. I added a large block of heap memory (via pvPortMalloc) and used it as the source for my SD card block writes, to my dismay the fwrite() function went from 2ms to 70ms for a 16kB block write. I then realized that the cache was probably getting clobbered due to the task stacks and other memory requirements while the block was being written to the SD card and the memory manager is probably thrashing.
To resolve the issue I added a 16kB internal SRAM block and copied a block from the heap block to the internal SRAM block and called fwrite() with said block and the 2ms write times were restored. The penalty for coping the data block is about 1ms so in total the SD card write now takes 3ms as opposed to 70ms.

My question: Is there a document or web page I can use as a reference to designing a better system when using the 4MB SPI SRAM?
I understand there is a performance penalty to using the SPI SRAM but there must be some tips available increase performance.

Regards,
Charles