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#define PIN_NUM_MOSI 23
#define PIN_NUM_MISO 19
#define PIN_NUM_CLK  18
#define PIN_NUM_CS   5

static spi_bus_config_t buscfg = {
    .miso_io_num = PIN_NUM_MISO,
    .mosi_io_num = PIN_NUM_MOSI,
    .sclk_io_num = PIN_NUM_CLK,
    .quadwp_io_num = -1,
    .quadhd_io_num = -1
};

static spi_slave_interface_config_t slvcfg = {
    .mode = 0,					// SPI mode0: CPOL=0, CPHA=0.
    .spics_io_num = PIN_NUM_CS,	// CS pin.
    .queue_size = 2,				// We want to be able to queue 2 transactions at a time.
    .flags = 0,
    //.post_setup_cb=my_post_setup_cb,
    //.post_trans_cb=my_post_trans_cb
};

static spi_slave_transaction_t *trans_buff0;
static spi_slave_transaction_t *trans_buff1;

...

spi_tx_buff = (uint8_t*) heap_caps_malloc(4092, MALLOC_CAP_DMA);
spi_rx_buff = (uint8_t*) heap_caps_malloc(4092, MALLOC_CAP_DMA);
trans_buff0 = (spi_slave_transaction_t *) malloc (sizeof(spi_slave_transaction_t));
trans_buff1 = (spi_slave_transaction_t *) malloc (sizeof(spi_slave_transaction_t));
...

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trans_buff0->rx_buffer = spi_rx_buff0;
trans_buff0->tx_buffer = spi_tx_buff0;
trans_buff0->length = SPI_PACKET_MAX_SIZE*8;
trans_buff0->user=&trans_id0;	
	
trans_buff1->rx_buffer = spi_rx_buff1;
trans_buff1->tx_buffer = spi_tx_buff1;
trans_buff1->length = SPI_PACKET_MAX_SIZE*8;
trans_buff1->user=&trans_id1;	

ret = spi_slave_queue_trans(VSPI_HOST, trans_buff0, 20/portTICK_RATE_MS);
assert(ret==ESP_OK);
ret = spi_slave_queue_trans(VSPI_HOST, trans_buff1, 20/portTICK_RATE_MS);
assert(ret==ESP_OK);

for(;;) {
	ret = spi_slave_get_trans_result(VSPI_HOST, &trans_rx, portMAX_DELAY);
	
	if(trans_rx == trans_buff0) {
		...
		ret = spi_slave_queue_trans(VSPI_HOST, trans_buff0, 20/portTICK_RATE_MS);
		assert(ret==ESP_OK);
	}
	
	if(trans_rx == trans_buff1) {
		...
		ret = spi_slave_queue_trans(VSPI_HOST, trans_buff1, 20/portTICK_RATE_MS);
		assert(ret==ESP_OK);
	}

}