ESP32 Forum

Hi to everyone !!
I'm using the ESP32 as I2C slave, connected to a master that polls the ESP so frequently.

My problem :
When the master reads from ESP and the ESP fifo is empty, the ESP responds garbage to the master.

In my opinion, when the master tries to read from slave (ESP32) and the slave has no data to respond (it means, the function
i2c_slave_write_buffer() is not called yet) , the slave should produce a NACK.

-->> How can I produce a NACK when the master tries to read from ESP32 and the function
i2c_slave_write_buffer is not called yet ?

Thank you !!

Although this is an old post I figured I'd update it in case anyone else stumbles upon it.
I've been struggling with this for the past week (ESP IDF 5.0.1, ESP32-S3-WROOM-1-N8R2) and my conclusion is

- When the i2c hardware transmit fifo (32 bytes) is empty the ESP32 transmits random(ish) garbage - I have not found any way to prevent this
- I did try modifying `i2c_isr_handler_default` to prefill the tx fifo with all zeros if the tx empty interrupt occurs and the tx ring buffer is empty (snippet below). This works, in as much as it prevents random responses from being sent to the host but .....
- We are running FatFS on the SPI flash - during erase/write cycles interrupts can be delayed up to 500ms unless you put the i2c handler into IRAM (see https://docs.espressif.com/projects/esp ... t-handlers)
- However the application is still blocked for up to 500ms at a time.

My conclusion is that the only way to deal with this (severe and ongoing) weakness of the ESP32 i2c hardware (sending garbage, not NAK) is to design the protocol and host to detect corrupt data using a CRC, checksum or similar).