ESP32 Forum

Posted: **Tue Jan 07, 2025 6:38 pm**

I have a serious problem with an ESP32-S3 based project, which needs to run a long time on a single battery. I have programmed everything using ESP-IDF 5.1.1 in Eclipse.

The main program does some calculations, starts the ULP program and then we go to esp_deep_sleep_start(). The ULP periodically sets some pins to high, takes ADC measurements and sets the pins to low again. After many measurements, the main processor is woken up an the cycle repeats.

I use the wemos S3 mini board which has the ESP32-S3FH4R2. For all following numbers I have removed the voltage regulator and the RGB-LED which can cause quite a bit of current draw and powered the bare board with 3.3 V directly. The current is measured via the Power Profiler Kit II (PPK2) by Nordic, which I have tested and found to be very accurate.

My problem: The datasheet promises 8 µA current consumption in Deep-sleep (RTC memory and RTC peripherals are powered up). On the first board I got 19 µA which would still be OK for me. Then I bought about 20 more for the project and they all were around 50 µA which is way too much. I even swapped the 50 µA ESP onto the board where I had measured the 19 µA to rule out everything but the chip itself. It is the chip. The plotted current consuption is attached.

I bought a while later another board which had 18 µA. So I bought 20 more boards which were all 50 µA again...

Here are some of the batch numbers and measured currents in deep sleep:
142023 - 19 µA
272023 - 50 µA
502023 - 18 µA
132024 - 50 µA

I would really appreciate a solution for my boards, since I have spent well over 200 € for them and I can't use them like this.

Posted: **Wed Jan 08, 2025 1:30 am**

What if you try a basic deep sleep test? No ULP, no ADC, aiming for constant load at the nominal ~8uA. Is there still a difference between batches?

Posted: **Wed Jan 08, 2025 11:24 am**

Thank you, that is a good test, should have thought of that myself. I removed everything that would cause changes after deep sleep and now all 4 batches are around 8 µA in deep sleep, as they should be.

On one of the boards that had 50 µA before, I then re-activated step by step different parts that affect the ULP operation to narrow down the problem: The additional current comes from enabling the ADC in ULP. Just enabling it in the main code, the ULP program is not running. These are the lines that make the difference:

Code: Select all

ulp_adc_cfg_t cfg = {
	.adc_n    = ADC_UNIT_1,
	.width    = ADC_BITWIDTH_DEFAULT,
	.atten    = ADC_ATTEN_DB_11,
	.ulp_mode = ADC_ULP_MODE_FSM,
};
ulp_adc_init(&cfg);

What can I do to fix that? For the final application I need the ADC only every few minutes, is there maybe a way of enabling it from the ULP? A full wakeup is not an option, since that consumes way too much power.

Posted: **Wed Jan 08, 2025 12:55 pm**

Try doing the equivalent of this from the ULP (L55-56 to turn on, L58-59 to turn off):
https://github.com/espressif/esp-idf/bl ... .h#L54-L59

You need to be very careful not to mess with these while awake as it could obviously interfere with any ADC operations the SOC is waiting for if they happen to coincide, such as in RF initialisation, RNG, etc.

You might also be able to call sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM) immediately before sleeping although I know this doesn't work well for ESP32 ULP ADC. Maybe it's better on S3?

Posted: **Wed Jan 08, 2025 9:55 pm**

Thank you very much. I don't have that much experience with ESPs yet, could you please explain a bit more what I need to do to implement your two approaches?

Posted: **Fri Jan 10, 2025 11:19 am**

Unfortunately, there is no good way to deal with this. The ADC will draw extra power when in deep sleep, unless it is turned off before entering sleep. Turning it off and on from the ULP has had some concerns regarding reliability of the ADC measurements.

Posted: **Mon Jan 13, 2025 11:17 am**

I am in too deep in this project now, I have to get it working. I would really like to try to turn the ADC on/off from ULP and thoroughly test it. Can someone tell me how I can implement that on the ULP?

Posted: **Mon Jan 13, 2025 11:54 am**

If the register structs are defined for the RISCV ULP then you should be able to copy the above linked lines exactly as they are, otherwise I'm pretty sure these macros will do the job:

Code: Select all

// Power down
REG_SET_FIELD(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0x2);
// Power up
REG_SET_FIELD(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0x3);

Posted: **Mon Jan 13, 2025 12:36 pm**

Sorry, I forgot to mention that I am using ULP-FSM not RISCV. Is the same possible there?

Posted: **Wed Jan 22, 2025 7:07 pm**

Ok, so I looked into this more and came up with the following lines to disable the ADC from ULP.

Code: Select all

WRITE_RTC_REG(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_SARADC_CLK_EN_S, 1, 0)
WRITE_RTC_REG(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_IOMUX_CLK_EN_S, 1, 0)
WRITE_RTC_REG(SENS_SAR_POWER_XPD_SAR_REG, SENS_SARCLK_EN_S, 1, 0)
WRITE_RTC_REG(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR_S, 2, 2)
WAIT 1000000

I tried pretty much all combinations of these lines without any effect on the current consumption.

Am I doing something wrong?

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