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ESP32-S3 secure boot 2 after develoment (new signing key), revoke fuse burnt?

http://esp32.io/viewtopic.php?f=13&t=43164

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ESP32-S3 secure boot 2 after develoment (new signing key), revoke fuse burnt?

Posted: Fri Nov 22, 2024 8:04 am
by jldesigns
Hello.
I've jumped on the project to finish up development of a ESP32-S3 device. The guy before me left a code base with a project and a script to build development and release.
We have around few dosen test devices with development signing keys. The guy assured me that it will be possible to change the key after development but only once. However I'm struggling to do it.

As You can see below It has a secure boot 2 enabled and a SECURE_BOOT_DIGEST0 for development key. However it has SECURE_BOOT_KEY_REVOKE1 and SECURE_BOOT_KEY_REVOKE2 fuse burnt. Now sure why (I don't think it was intentional).
Burnin a new SECURE_BOOT_DIGEST0 does not seems to work (i don't think it should). And using SECURE_BOOT_DIGEST1 and SECURE_BOOT_DIGEST2 seams not possible since the revoked fuses are burnt (however they seems to be R/W still).

Can anybody confirm or deny if its possible to use new signing key?
Why the SECURE_BOOT_KEY_REVOKE1 and SECURE_BOOT_KEY_REVOKE2 are burned Probably bootloader did it, but why?

This is a efuse summary of sample device used for development:
Code: [Select all] [Expand/Collapse]
  1. espefuse.py v4.7.0
  2. Connecting....
  3. Detecting chip type... ESP32-S3
  4.  
  5. === Run "summary" command ===
  6. EFUSE_NAME (Block) Description  = [Meaningful Value] [Readable/Writeable] (Hex Value)
  7. ----------------------------------------------------------------------------------------
  8. Calibration fuses:
  9. K_RTC_LDO (BLOCK1)                                 BLOCK1 K_RTC_LDO                                   = 52 R/W (0b0001101)
  10. K_DIG_LDO (BLOCK1)                                 BLOCK1 K_DIG_LDO                                   = -64 R/W (0b1010000)
  11. V_RTC_DBIAS20 (BLOCK1)                             BLOCK1 voltage of rtc dbias20                      = 80 R/W (0x14)
  12. V_DIG_DBIAS20 (BLOCK1)                             BLOCK1 voltage of digital dbias20                  = -100 R/W (0x99)
  13. DIG_DBIAS_HVT (BLOCK1)                             BLOCK1 digital dbias when hvt                      = -44 R/W (0b11011)
  14. ADC2_CAL_VOL_ATTEN3 (BLOCK1)                       ADC2 calibration voltage at atten3                 = -24 R/W (0b100110)
  15. TEMP_CALIB (BLOCK2)                                Temperature calibration data                       = -6.6000000000000005 R/W (0b101000010)
  16. OCODE (BLOCK2)                                     ADC OCode                                          = 79 R/W (0x4f)
  17. ADC1_INIT_CODE_ATTEN0 (BLOCK2)                     ADC1 init code at atten0                           = -92 R/W (0x97)
  18. ADC1_INIT_CODE_ATTEN1 (BLOCK2)                     ADC1 init code at atten1                           = 0 R/W (0b100000)
  19. ADC1_INIT_CODE_ATTEN2 (BLOCK2)                     ADC1 init code at atten2                           = 92 R/W (0b010111)
  20. ADC1_INIT_CODE_ATTEN3 (BLOCK2)                     ADC1 init code at atten3                           = 116 R/W (0b011101)
  21. ADC2_INIT_CODE_ATTEN0 (BLOCK2)                     ADC2 init code at atten0                           = -196 R/W (0xb1)
  22. ADC2_INIT_CODE_ATTEN1 (BLOCK2)                     ADC2 init code at atten1                           = -8 R/W (0b100010)
  23. ADC2_INIT_CODE_ATTEN2 (BLOCK2)                     ADC2 init code at atten2                           = 64 R/W (0b010000)
  24. ADC2_INIT_CODE_ATTEN3 (BLOCK2)                     ADC2 init code at atten3                           = 96 R/W (0b011000)
  25. ADC1_CAL_VOL_ATTEN0 (BLOCK2)                       ADC1 calibration voltage at atten0                 = -16 R/W (0x84)
  26. ADC1_CAL_VOL_ATTEN1 (BLOCK2)                       ADC1 calibration voltage at atten1                 = 508 R/W (0x7f)
  27. ADC1_CAL_VOL_ATTEN2 (BLOCK2)                       ADC1 calibration voltage at atten2                 = 448 R/W (0x70)
  28. ADC1_CAL_VOL_ATTEN3 (BLOCK2)                       ADC1 calibration voltage at atten3                 = -24 R/W (0x86)
  29. ADC2_CAL_VOL_ATTEN0 (BLOCK2)                       ADC2 calibration voltage at atten0                 = -32 R/W (0x88)
  30. ADC2_CAL_VOL_ATTEN1 (BLOCK2)                       ADC2 calibration voltage at atten1                 = -4 R/W (0b1000001)
  31. ADC2_CAL_VOL_ATTEN2 (BLOCK2)                       ADC2 calibration voltage at atten2                 = -16 R/W (0b1000100)
  32.  
  33. Config fuses:
  34. WR_DIS (BLOCK0)                                    Disable programming of individual eFuses           = 58722049 R/W (0x03800701)
  35. RD_DIS (BLOCK0)                                    Disable reading from BlOCK4-10                     = 6 R/- (0b0000110)
  36. DIS_ICACHE (BLOCK0)                                Set this bit to disable Icache                     = False R/W (0b0)
  37. DIS_DCACHE (BLOCK0)                                Set this bit to disable Dcache                     = False R/W (0b0)
  38. DIS_TWAI (BLOCK0)                                  Set this bit to disable CAN function               = False R/W (0b0)
  39. DIS_APP_CPU (BLOCK0)                               Disable app cpu                                    = False R/W (0b0)
  40. DIS_DIRECT_BOOT (BLOCK0)                           Disable direct boot mode                           = True R/W (0b1)
  41. UART_PRINT_CONTROL (BLOCK0)                        Set the default UART boot message output mode      = Enable R/W (0b00)
  42. PIN_POWER_SELECTION (BLOCK0)                       Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0)
  43.                                                    en SPI flash is initialized                      
  44. PSRAM_CAP (BLOCK1)                                 PSRAM capacity                                     = None R/W (0b00)
  45. PSRAM_TEMP (BLOCK1)                                PSRAM temperature                                  = None R/W (0b00)
  46. PSRAM_VENDOR (BLOCK1)                              PSRAM vendor                                       = None R/W (0b00)
  47. BLOCK_USR_DATA (BLOCK3)                            User data                                        
  48.    = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
  49. BLOCK_SYS_DATA2 (BLOCK10)                          System data part 2 (reserved)                    
  50.    = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
  51.  
  52. Flash fuses:
  53. FLASH_TPUW (BLOCK0)                                Configures flash waiting time after power-up; in u = 0 R/W (0x0)
  54.                                                    nit of ms. If the value is less than 15; the waiti
  55.                                                    ng time is the configurable value.  Otherwise; the
  56.                                                     waiting time is twice the configurable value    
  57. FLASH_ECC_MODE (BLOCK0)                            Flash ECC mode in ROM                              = 16to18 byte R/W (0b0)
  58. FLASH_TYPE (BLOCK0)                                SPI flash type                                     = 4 data lines R/W (0b0)
  59. FLASH_PAGE_SIZE (BLOCK0)                           Set Flash page size                                = 0 R/W (0b00)
  60. FLASH_ECC_EN (BLOCK0)                              Set 1 to enable ECC for flash boot                 = False R/W (0b0)
  61. FORCE_SEND_RESUME (BLOCK0)                         Set this bit to force ROM code to send a resume co = False R/W (0b0)
  62.                                                    mmand during SPI boot                            
  63. FLASH_CAP (BLOCK1)                                 Flash capacity                                     = None R/W (0b000)
  64. FLASH_TEMP (BLOCK1)                                Flash temperature                                  = None R/W (0b00)
  65. FLASH_VENDOR (BLOCK1)                              Flash vendor                                       = None R/W (0b000)
  66.  
  67. Identity fuses:
  68. DISABLE_WAFER_VERSION_MAJOR (BLOCK0)               Disables check of wafer version major              = False R/W (0b0)
  69. DISABLE_BLK_VERSION_MAJOR (BLOCK0)                 Disables check of blk version major                = False R/W (0b0)
  70. WAFER_VERSION_MINOR_LO (BLOCK1)                    WAFER_VERSION_MINOR least significant bits         = 1 R/W (0b001)
  71. PKG_VERSION (BLOCK1)                               Package version                                    = 0 R/W (0b000)
  72. BLK_VERSION_MINOR (BLOCK1)                         BLK_VERSION_MINOR                                  = 2 R/W (0b010)
  73. WAFER_VERSION_MINOR_HI (BLOCK1)                    WAFER_VERSION_MINOR most significant bit           = False R/W (0b0)
  74. WAFER_VERSION_MAJOR (BLOCK1)                       WAFER_VERSION_MAJOR                                = 0 R/W (0b00)
  75. OPTIONAL_UNIQUE_ID (BLOCK2)                        Optional unique 128-bit ID                        
  76.    = b5 81 d4 fe 9f 65 5c fd b6 6b 5e ef b5 6d 19 ba R/W
  77. BLK_VERSION_MAJOR (BLOCK2)                         BLK_VERSION_MAJOR of BLOCK2                        = ADC calib V1 R/W (0b01)
  78. WAFER_VERSION_MINOR (BLOCK0)                       calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI  = 1 R/W (0x1)
  79.                                                    << 3 + WAFER_VERSION_MINOR_LO (read only)        
  80.  
  81. Jtag fuses:
  82. SOFT_DIS_JTAG (BLOCK0)                             Set these bits to disable JTAG in the soft way (od = 7 R/W (0b111)
  83.                                                    d number 1 means disable ). JTAG can be enabled in
  84.                                                     HMAC module                                      
  85. DIS_PAD_JTAG (BLOCK0)                              Set this bit to disable JTAG in the hard way. JTAG = True R/W (0b1)
  86.                                                     is disabled permanently                          
  87. STRAP_JTAG_SEL (BLOCK0)                            Set this bit to enable selection between usb_to_jt = False R/W (0b0)
  88.                                                    ag and pad_to_jtag through strapping gpio10 when b
  89.                                                    oth reg_dis_usb_jtag and reg_dis_pad_jtag are equa
  90.                                                    l to 0                                            
  91.  
  92. Mac fuses:
  93. MAC (BLOCK1)                                       MAC address                                      
  94.    = 34:85:18:52:5c:00 (OK) R/W
  95. CUSTOM_MAC (BLOCK3)                                Custom MAC                                        
  96.    = 00:00:00:00:00:00 (OK) R/W
  97.  
  98. Security fuses:
  99. DIS_DOWNLOAD_ICACHE (BLOCK0)                       Set this bit to disable Icache in download mode (b = True R/W (0b1)
  100.                                                    oot_mode[3:0] is 0; 1; 2; 3; 6; 7)                
  101. DIS_DOWNLOAD_DCACHE (BLOCK0)                       Set this bit to disable Dcache in download mode (  = True R/W (0b1)
  102.                                                    boot_mode[3:0] is 0; 1; 2; 3; 6; 7)              
  103. DIS_FORCE_DOWNLOAD (BLOCK0)                        Set this bit to disable the function that forces c = False R/W (0b0)
  104.                                                    hip into download mode                            
  105. DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0)               Set this bit to disable flash encryption when in d = False R/W (0b0)
  106.                                                    ownload boot modes                                
  107. SPI_BOOT_CRYPT_CNT (BLOCK0)                        Enables flash encryption when 1 or 3 bits are set  = Enable R/W (0b001)
  108.                                                    and disabled otherwise                            
  109. SECURE_BOOT_KEY_REVOKE0 (BLOCK0)                   Revoke 1st secure boot key                         = False R/W (0b0)
  110. SECURE_BOOT_KEY_REVOKE1 (BLOCK0)                   Revoke 2nd secure boot key                         = True R/W (0b1)
  111. SECURE_BOOT_KEY_REVOKE2 (BLOCK0)                   Revoke 3rd secure boot key                         = True R/W (0b1)
  112. KEY_PURPOSE_0 (BLOCK0)                             Purpose of Key0                                    = SECURE_BOOT_DIGEST0 R/- (0x9)
  113. KEY_PURPOSE_1 (BLOCK0)                             Purpose of Key1                                    = XTS_AES_256_KEY_1 R/- (0x2)
  114. KEY_PURPOSE_2 (BLOCK0)                             Purpose of Key2                                    = XTS_AES_256_KEY_2 R/- (0x3)
  115. KEY_PURPOSE_3 (BLOCK0)                             Purpose of Key3                                    = USER R/W (0x0)
  116. KEY_PURPOSE_4 (BLOCK0)                             Purpose of Key4                                    = USER R/W (0x0)
  117. KEY_PURPOSE_5 (BLOCK0)                             Purpose of Key5                                    = USER R/W (0x0)
  118. SECURE_BOOT_EN (BLOCK0)                            Set this bit to enable secure boot                 = True R/W (0b1)
  119. SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0)             Set this bit to enable revoking aggressive secure  = False R/W (0b0)
  120.                                                    boot                                              
  121. DIS_DOWNLOAD_MODE (BLOCK0)                         Set this bit to disable download mode (boot_mode[3 = False R/W (0b0)
  122.                                                    :0] = 0; 1; 2; 3; 6; 7)                          
  123. ENABLE_SECURITY_DOWNLOAD (BLOCK0)                  Set this bit to enable secure UART download mode   = False R/W (0b0)
  124. SECURE_VERSION (BLOCK0)                            Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000)
  125.                                                    ure)                                              
  126. BLOCK_KEY0 (BLOCK4)
  127.   Purpose: SECURE_BOOT_DIGEST0
  128.   Key0 or user data                                
  129.    = 0b aa 7f 66 16 11 01 b1 c3 ee 6b 78 d8 ab 38 dc 20 ae fb e9 43 9e 87 ce 86 44 a7 bd 20 c7 ef fb R/-
  130. BLOCK_KEY1 (BLOCK5)
  131.   Purpose: XTS_AES_256_KEY_1
  132.   Key1 or user data                                
  133.    = ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? -/-
  134. BLOCK_KEY2 (BLOCK6)
  135.   Purpose: XTS_AES_256_KEY_2
  136.   Key2 or user data                                
  137.    = ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? -/-
  138. BLOCK_KEY3 (BLOCK7)
  139.   Purpose: USER
  140.                Key3 or user data                                
  141.    = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
  142. BLOCK_KEY4 (BLOCK8)
  143.   Purpose: USER
  144.                Key4 or user data                                
  145.    = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
  146. BLOCK_KEY5 (BLOCK9)
  147.   Purpose: USER
  148.                Key5 or user data                                
  149.    = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
  150.  
  151. Spi Pad fuses:
  152. SPI_PAD_CONFIG_CLK (BLOCK1)                        SPI_PAD_configure CLK                              = 0 R/W (0b000000)
  153. SPI_PAD_CONFIG_Q (BLOCK1)                          SPI_PAD_configure Q(D1)                            = 0 R/W (0b000000)
  154. SPI_PAD_CONFIG_D (BLOCK1)                          SPI_PAD_configure D(D0)                            = 0 R/W (0b000000)
  155. SPI_PAD_CONFIG_CS (BLOCK1)                         SPI_PAD_configure CS                               = 0 R/W (0b000000)
  156. SPI_PAD_CONFIG_HD (BLOCK1)                         SPI_PAD_configure HD(D3)                           = 0 R/W (0b000000)
  157. SPI_PAD_CONFIG_WP (BLOCK1)                         SPI_PAD_configure WP(D2)                           = 0 R/W (0b000000)
  158. SPI_PAD_CONFIG_DQS (BLOCK1)                        SPI_PAD_configure DQS                              = 0 R/W (0b000000)
  159. SPI_PAD_CONFIG_D4 (BLOCK1)                         SPI_PAD_configure D4                               = 0 R/W (0b000000)
  160. SPI_PAD_CONFIG_D5 (BLOCK1)                         SPI_PAD_configure D5                               = 0 R/W (0b000000)
  161. SPI_PAD_CONFIG_D6 (BLOCK1)                         SPI_PAD_configure D6                               = 0 R/W (0b000000)
  162. SPI_PAD_CONFIG_D7 (BLOCK1)                         SPI_PAD_configure D7                               = 0 R/W (0b000000)
  163.  
  164. Usb fuses:
  165. DIS_USB_OTG (BLOCK0)                               Set this bit to disable USB function               = False R/W (0b0)
  166. USB_EXCHG_PINS (BLOCK0)                            Set this bit to exchange USB D+ and D- pins        = False R/W (0b0)
  167. USB_EXT_PHY_ENABLE (BLOCK0)                        Set this bit to enable external PHY                = False R/W (0b0)
  168. DIS_USB_JTAG (BLOCK0)                              Set this bit to disable function of usb switch to  = True R/W (0b1)
  169.                                                    jtag in module of usb device                      
  170. DIS_USB_SERIAL_JTAG (BLOCK0)                       Set this bit to disable usb device                 = False R/W (0b0)
  171. USB_PHY_SEL (BLOCK0)                               This bit is used to switch internal PHY and extern
  172.    = internal PHY is assigned to USB Device while external PHY is assigned to USB OTG R/W (0b0)
  173.                                                    al PHY for USB OTG and USB Device                
  174. DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0)             USB printing                                       = Enable R/W (0b0)
  175. DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0)         Set this bit to disable UART download mode through = False R/W (0b0)
  176.                                                     USB                                              
  177. DIS_USB_OTG_DOWNLOAD_MODE (BLOCK0)                 Set this bit to disable download through USB-OTG   = False R/W (0b0)
  178.  
  179. Vdd fuses:
  180. VDD_SPI_XPD (BLOCK0)                               SPI regulator power up signal                      = False R/W (0b0)
  181. VDD_SPI_TIEH (BLOCK0)                              If VDD_SPI_FORCE is 1; determines VDD_SPI voltage
  182.    = VDD_SPI connects to 1.8 V LDO R/W (0b0)
  183. VDD_SPI_FORCE (BLOCK0)                             Set this bit and force to use the configuration of = False R/W (0b0)
  184.                                                     eFuse to configure VDD_SPI                      
  185.  
  186. Wdt fuses:
  187. WDT_DELAY_SEL (BLOCK0)                             RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00)
  188.                                                    ock cycle                                        
  189.  
  190. Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO
  191. GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V).
GeSHi © Codebox Plus Extension
Code: [Select all] [Expand/Collapse]
  1. CONFIG_IDF_TARGET="esp32s3"
  2. CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE=y
  3. CONFIG_SECURE_BOOT=y
  4. CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE=y
  5. CONFIG_SECURE_DISABLE_ROM_DL_MODE=y
  6. CONFIG_SECURE_BOOT_SIGNING_KEY="main/security/secure_boot/rel/secure_boot_key_0.pem"
  7. CONFIG_LOG_DEFAULT_LEVEL_ERROR=y
  8. CONFIG_TARGET_DEVICE_RELEASE_BUILD=y
  9. CONFIG_SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT=y
  10. CONFIG_SECURE_FLASH_ENC_ENABLED=y
  11. CONFIG_SECURE_FLASH_ENCRYPTION_AES256=y
  12. CONFIG_ESPTOOLPY_FLASHSIZE_16MB=y
  13. CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
  14. CONFIG_PARTITION_TABLE_CUSTOM=y
  15. CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
  16. CONFIG_PARTITION_TABLE_OFFSET=0x10000
  17. CONFIG_COMPILER_OPTIMIZATION_SIZE=y
  18. CONFIG_BT_ENABLED=y
  19. CONFIG_BT_NIMBLE_ENABLED=y
  20. CONFIG_BT_NIMBLE_MAX_CONNECTIONS=1
  21. CONFIG_BT_NIMBLE_MAX_BONDS=2
  22. CONFIG_BT_NIMBLE_MAX_CCCDS=4
  23. CONFIG_BT_NIMBLE_ATT_PREFERRED_MTU=512
  24. CONFIG_ESP_MAIN_TASK_STACK_SIZE=4096
  25. CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y
  26. CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744
  27. CONFIG_LWIP_TCP_WND_DEFAULT=5744
  28. CONFIG_TARGET_DEVICE_CERT_TYPE="REL"
GeSHi © Codebox Plus Extension
Code: [Select all] [Expand/Collapse]
  1. CONFIG_IDF_TARGET="esp32s3"
  2. CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE=y
  3. CONFIG_SECURE_BOOT=y
  4. CONFIG_SECURE_BOOT_SIGNING_KEY="main/security/secure_boot/dev/secure_boot_key_0.pem"
  5. CONFIG_LOG_DEFAULT_LEVEL_INFO=y
  6. CONFIG_FREERTOS_USE_TRACE_FACILITY=y
  7. CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y
  8. CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID=y
  9. CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID=y
  10. CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=y
  11. CONFIG_SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT=y
  12. CONFIG_SECURE_FLASH_ENC_ENABLED=y
  13. CONFIG_SECURE_FLASH_ENCRYPTION_AES256=y
  14. CONFIG_ESPTOOLPY_FLASHSIZE_16MB=y
  15. CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
  16. CONFIG_PARTITION_TABLE_CUSTOM=y
  17. CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
  18. CONFIG_PARTITION_TABLE_OFFSET=0x10000
  19. CONFIG_COMPILER_OPTIMIZATION_SIZE=y
  20. CONFIG_BT_ENABLED=y
  21. CONFIG_BT_NIMBLE_ENABLED=y
  22. CONFIG_BT_NIMBLE_MAX_CONNECTIONS=1
  23. CONFIG_BT_NIMBLE_MAX_BONDS=2
  24. CONFIG_BT_NIMBLE_MAX_CCCDS=4
  25. CONFIG_BT_NIMBLE_ATT_PREFERRED_MTU=512
  26. CONFIG_ESP_MAIN_TASK_STACK_SIZE=4096
  27. CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y
  28. CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744
  29. CONFIG_LWIP_TCP_WND_DEFAULT=5744
  30. CONFIG_TARGET_DEVICE_CERT_TYPE="DEV"
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