RISC-V ULP interrupt context saving
Posted: Tue Nov 19, 2024 1:58 pm
In ESP32-S3 RISC-V ULP interrupt code (ulp/ulp_riscv/ulp_core/ulp_riscv_vector.S), there is a note saying:
This causes some issues that the riscv32-esp-elf-gcc generated code do used s registers for function local variables. If I manually add saving/restore of s0-s11 then the issue is solved.
Is there an "elegant" way to solve this without touch the esp-idf code base?
Thanks
Baoshi
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Note: We don't save the callee-saved s0-s11 registers to save space
Is there an "elegant" way to solve this without touch the esp-idf code base?
Thanks
Baoshi