ESP32 Forum

I'm using ESP32-S3 with QSPI flash and OSPI RAM. My ESP32-S3's internal ram are heavily used, and during QSPI updates(not sure if erase or write) my 250kbps UART ISR cannot empty the FIFO, and my thread gets FIFO errors. Would it make sense to move the involved functions into PSRAM, as I'm low on IRAM? I don't want to move everything using CONFIG_SPIRAM_FETCH_INSTRUCTIONS, is there a word like "noflash" for linker-fragment files, but that would move to psram instead?

PSRAM is accessed through the cache just as flash is. During flash writes the cache is disabled/inaccessible, so neither code from flash nor from PSRAM would be available, leaving (internal) IRAM and ROM as the only places to run code from while updating flash.

Thanks, I see now how the caches are connected in the TRM. I was hoping the ESP32-S3's dual caches would be connected as one cache for the Flash, and one for the PSRAM, and that perhaps PSRAM accesses could continue during Flash erase/programming operations, but I no longer think that would be the case.