ESP32 Forum

I just want to implement the simple bitwise logical operation as seen in below schematic:
Register bit count may vary. Thanks.

...okay, can you give a bit more context? How fast does it need to be, why do you want an edge detector like that in the first place?

Hello,

...okay, can you give a bit more context? How fast does it need to be,

Speed is very low, 1200 baud

My drawing is just a case. I want to learn the principles. Instead of sampling the input with a clock source, i can use interrupt to detect the input change.

My actual aim is to make a Manchester Encoder - Decoder in the end. Manchester encoding is just y(n)=x(n) XOR x(n-1). I found a solution made with the RMT here in this forum (viewtopic.php?f=19&t=9234&hilit=manchester ) , Of course I can write a C task for this purpose as well but I am looking for alternative and simpler methods.

All solution suggestions are valuable to me; Instead of asking new questions you can suggest a solution based on how you understand it and how you think it would be better. Thanks.

I guess in addition to a GPIO change interrupt you'll also need some 'clock'/timer to react when the input is constant.
Here's what I would do:
1. Set up a one-shot timer which runs out in 1/1200 seconds, don't start the timer yet. In the timer callback, you simply send a '0' to the output pin.
1. Configure an interrupt to be triggered when the input pin changes state ("ANYEDGE").
2. When this interrupt gets triggered you know that a change on the input happened so you send a '1' to the output, reset the timer and start it.

This might need a little bit of fiddling with the timer duration and/or a way to inhibit the timer to avoid glitches in the output (when the timer expires around the same time the next input signal change happens.)

Another option would of course be to only use a periodic timer at 1/1200 seconds; sample the input pin in the timer callback, xor with the previuos output and output the result. This is the exact analog to the hardware edge detector, with the timer generating the CK. Like the hardware solution, it has its problems depending on the exact frequency and phase relation of the input signal and the timer.
The GPIO interrupt + timer approach mitigates the issue by 'synchronizing' the phase, but not frequency, of the CK to the phase of the input signal.